diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
index 5b2ec14388..ce692133a0 100644
--- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
@@ -20,11 +20,6 @@ chip soc/intel/alderlake
 	# DPTF enable
 	register "dptf_enable" = "1"
 
-	register "power_limits_config" = "{
-		.tdp_pl1_override = 15,
-		.tdp_pl2_override = 55,
-	}"
-
 	# Enable heci communication
 	register "HeciEnabled" = "1"
 
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index 9def4be7d3..ad7c971f0d 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -134,11 +134,6 @@ chip soc/intel/alderlake
 	register "s0ix_enable" = "1"
 	register "dptf_enable" = "1"
 
-	register "power_limits_config" = "{
-		.tdp_pl1_override = 45,
-		.tdp_pl2_override = 56,
-	}"
-
 	register "SerialIoI2cMode" = "{
 		[PchSerialIoIndexI2C0] = PchSerialIoPci,
 		[PchSerialIoIndexI2C1] = PchSerialIoPci,
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 57b78688ee..853de1cccb 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -17,13 +17,22 @@
 #include <soc/usb.h>
 #include <stdint.h>
 
+/* Types of different SKUs */
+enum soc_intel_alderlake_power_limits {
+	ADL_P_POWER_LIMITS_282_CORE,
+	ADL_P_POWER_LIMITS_482_CORE,
+	ADL_P_POWER_LIMITS_682_CORE,
+	ADL_M_POWER_LIMITS_282_CORE,
+	ADL_POWER_LIMITS_COUNT
+};
+
 struct soc_intel_alderlake_config {
 
 	/* Common struct containing soc config data required by common code */
 	struct soc_intel_common_config common_soc_config;
 
 	/* Common struct containing power limits configuration information */
-	struct soc_power_limits_config power_limits_config;
+	struct soc_power_limits_config power_limits_config[ADL_POWER_LIMITS_COUNT];
 
 	/* Gpio group routed to each dword of the GPE0 block. Values are
 	 * of the form PMC_GPP_[A:U] or GPD. */
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb
index c51f92caae..7085263b66 100644
--- a/src/soc/intel/alderlake/chipset.cb
+++ b/src/soc/intel/alderlake/chipset.cb
@@ -1,4 +1,25 @@
 chip soc/intel/alderlake
+
+	register "power_limits_config[ADL_P_POWER_LIMITS_282_CORE]" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 55,
+	}"
+
+	register "power_limits_config[ADL_P_POWER_LIMITS_482_CORE]" = "{
+		.tdp_pl1_override = 28,
+		.tdp_pl2_override = 64,
+	}"
+
+	register "power_limits_config[ADL_P_POWER_LIMITS_682_CORE]" = "{
+		.tdp_pl1_override = 45,
+		.tdp_pl2_override = 115,
+	}"
+
+	register "power_limits_config[ADL_M_POWER_LIMITS_282_CORE]" = "{
+		.tdp_pl1_override = 9,
+		.tdp_pl2_override = 30,
+	}"
+
 	device domain 0 on
 		device gpio 0 alias pch_gpio on end
 		device pci 00.0 alias system_agent on end
diff --git a/src/soc/intel/alderlake/systemagent.c b/src/soc/intel/alderlake/systemagent.c
index eb1defc87a..acdaded685 100644
--- a/src/soc/intel/alderlake/systemagent.c
+++ b/src/soc/intel/alderlake/systemagent.c
@@ -6,8 +6,10 @@
  * Chapter number: 3
  */
 
+#include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_ids.h>
 #include <delay.h>
 #include <intelblocks/power_limit.h>
 #include <intelblocks/systemagent.h>
@@ -52,6 +54,8 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index)
 void soc_systemagent_init(struct device *dev)
 {
 	struct soc_power_limits_config *soc_config;
+	struct device *sa;
+	uint16_t sa_pci_id;
 	config_t *config;
 
 	/* Enable Power Aware Interrupt Routing */
@@ -63,7 +67,32 @@ void soc_systemagent_init(struct device *dev)
 	/* Configure turbo power limits 1ms after reset complete bit */
 	mdelay(1);
 	config = config_of_soc();
-	soc_config = &config->power_limits_config;
+
+	/* Get System Agent PCI ID */
+	sa = pcidev_path_on_root(SA_DEVFN_ROOT);
+	sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF;
+
+	/* Choose a power limits configuration based on the SoC SKU type,
+	 * differentiated here based on SA PCI ID. */
+	switch (sa_pci_id) {
+	case PCI_DEVICE_ID_INTEL_ADL_P_ID_7:
+		soc_config = &config->power_limits_config[ADL_P_POWER_LIMITS_282_CORE];
+		break;
+	case PCI_DEVICE_ID_INTEL_ADL_P_ID_5:
+		soc_config = &config->power_limits_config[ADL_P_POWER_LIMITS_482_CORE];
+		break;
+	case PCI_DEVICE_ID_INTEL_ADL_P_ID_3:
+		soc_config = &config->power_limits_config[ADL_P_POWER_LIMITS_682_CORE];
+		break;
+	case PCI_DEVICE_ID_INTEL_ADL_M_ID_1:
+		soc_config = &config->power_limits_config[ADL_M_POWER_LIMITS_282_CORE];
+		break;
+	default:
+		printk(BIOS_ERR, "ADL: unknown SA ID: 0x%4x, skipping power limits configuration\n",
+			sa_pci_id);
+		return;
+	}
+
 	set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
 }