mb/*/*/early_init.c: Remove unused <device/pci_{def,ops}.h>
Change-Id: I4cd9d22d2105c270a3d1e8a0be40b594c7c8b226 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37687 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -13,8 +13,6 @@
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#include <stdint.h>
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#include <string.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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@ -15,7 +15,6 @@
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*/
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#include <bootblock_common.h>
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#include <device/pci_ops.h>
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#include <device/pnp_ops.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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@ -17,7 +17,6 @@
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#include <bootblock_common.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <device/pci_ops.h>
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#include <device/pnp_ops.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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@ -16,7 +16,6 @@
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#include <bootblock_common.h>
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#include <device/pnp_ops.h>
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#include <device/pci_ops.h>
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#include <device/dram/ddr3.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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@ -19,7 +19,6 @@
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#include <stdint.h>
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#include <cf9_reset.h>
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#include <device/pnp_ops.h>
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#include <device/pci_ops.h>
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#include <superio/winbond/common/winbond.h>
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#include <superio/winbond/w83627dhg/w83627dhg.h>
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#include <console/console.h>
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@ -15,7 +15,6 @@
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*/
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#include <bootblock_common.h>
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#include <device/pci_ops.h>
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#include <device/dram/ddr3.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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@ -14,7 +14,6 @@
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*/
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#include <bootblock_common.h>
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#include <device/pci_ops.h>
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#include <device/pnp_ops.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <device/pci_ops.h>
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#include <device/pnp_ops.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <bootblock_common.h>
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#include <stdint.h>
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#include <arch/io.h>
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#include <device/pci_ops.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <superio/smsc/sio1007/sio1007.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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*/
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#include <bootblock_common.h>
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#include <device/pci_ops.h>
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#include <southbridge/intel/i82801gx/i82801gx.h>
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#include <northbridge/intel/pineview/pineview.h>
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#include <superio/ite/common/ite.h>
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@ -14,7 +14,6 @@
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*/
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#include <bootblock_common.h>
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#include <device/pci_ops.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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*/
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#include <bootblock_common.h>
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#include <device/pci_ops.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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*/
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#include <stdint.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <cpu/x86/lapic.h>
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#include <arch/acpi.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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*/
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#include <stdint.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <cpu/x86/lapic.h>
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#include <arch/acpi.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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*/
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#include <stdint.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <cpu/x86/lapic.h>
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#include <arch/acpi.h>
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#include <console/console.h>
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*/
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#include <bootblock_common.h>
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#include <device/pci_ops.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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*/
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#include <bootblock_common.h>
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#include <device/pci_ops.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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*/
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#include <bootblock_common.h>
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#include <device/pci_ops.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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*/
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#include <bootblock_common.h>
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#include <device/pci_ops.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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*/
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#include <bootblock_common.h>
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#include <device/pci_ops.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <bootblock_common.h>
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#include <stdint.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <superio/nuvoton/npcd378/npcd378.h>
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#include <superio/nuvoton/common/nuvoton.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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*/
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#include <bootblock_common.h>
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#include <device/pci_ops.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <string.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <device/pci_ops.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <bootblock_common.h>
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#include <stdint.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <superio/nuvoton/npcd378/npcd378.h>
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#include <superio/nuvoton/common/nuvoton.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <bootblock_common.h>
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#include <stdint.h>
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#include <cf9_reset.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <console/console.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <bootblock_common.h>
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#include <stdint.h>
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#include <arch/io.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <cpu/x86/lapic.h>
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#include <superio/smsc/sio1007/sio1007.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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* GNU General Public License for more details.
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*/
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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* GNU General Public License for more details.
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*/
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <stdint.h>
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#include <string.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <cpu/x86/lapic.h>
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#include <console/console.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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*/
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#include <stdint.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <cpu/x86/lapic.h>
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#include <arch/acpi.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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*/
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#include <stdint.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <cpu/x86/lapic.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <stdint.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <bootblock_common.h>
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#include <stdint.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <device/pnp_ops.h>
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#include <device/pnp.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <string.h>
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#include <arch/io.h>
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#include <bootblock_common.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <cpu/x86/lapic.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <bootblock_common.h>
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#include <stdint.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <cpu/x86/lapic.h>
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#include <pc80/mc146818rtc.h>
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#include <console/console.h>
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