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mb/*/*/early_init.c: Remove unused <device/pci_{def,ops}.h> 

Change-Id: I4cd9d22d2105c270a3d1e8a0be40b594c7c8b226
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37687
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2019-12-13 08:36:20 +01:00 committed by Kyösti Mälkki
parent e5476db4aa
commit aa57187f82
35 changed files with 0 additions and 50 deletions
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2
src/mainboard/apple/macbookair4_2/early_init.c
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@ -13,8 +13,6 @@
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>

1
src/mainboard/asrock/b75pro3-m/early_init.c
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@ -15,7 +15,6 @@
*/ */
#include <bootblock_common.h> #include <bootblock_common.h>
#include <device/pci_ops.h>
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>

1
src/mainboard/asus/h61m-cs/early_init.c
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@ -17,7 +17,6 @@
#include <bootblock_common.h> #include <bootblock_common.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <device/pci_ops.h>
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>

1
src/mainboard/asus/maximus_iv_gene-z/early_init.c
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@ -16,7 +16,6 @@
#include <bootblock_common.h> #include <bootblock_common.h>
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
#include <device/pci_ops.h>
#include <device/dram/ddr3.h> #include <device/dram/ddr3.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>

1
src/mainboard/asus/p5gc-mx/early_init.c
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@ -19,7 +19,6 @@
#include <stdint.h> #include <stdint.h>
#include <cf9_reset.h> #include <cf9_reset.h>
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
#include <device/pci_ops.h>
#include <superio/winbond/common/winbond.h> #include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627dhg/w83627dhg.h> #include <superio/winbond/w83627dhg/w83627dhg.h>
#include <console/console.h> #include <console/console.h>

1
src/mainboard/asus/p8h61-m_lx/early_init.c
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@ -15,7 +15,6 @@
*/ */
#include <bootblock_common.h> #include <bootblock_common.h>
#include <device/pci_ops.h>
#include <device/dram/ddr3.h> #include <device/dram/ddr3.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>

1
src/mainboard/asus/p8h61-m_pro/early_init.c
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@ -14,7 +14,6 @@
*/ */
#include <bootblock_common.h> #include <bootblock_common.h>
#include <device/pci_ops.h>
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>

1
src/mainboard/asus/p8z77-m_pro/early_init.c
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@ -14,7 +14,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <bootblock_common.h> #include <bootblock_common.h>
#include <device/pci_ops.h>
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>

1
src/mainboard/compulab/intense_pc/early_init.c
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@ -16,7 +16,6 @@
#include <bootblock_common.h> #include <bootblock_common.h>
#include <stdint.h> #include <stdint.h>
#include <arch/io.h> #include <arch/io.h>
#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <superio/smsc/sio1007/sio1007.h> #include <superio/smsc/sio1007/sio1007.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>

1
src/mainboard/foxconn/d41s/early_init.c
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@ -16,7 +16,6 @@
*/ */
#include <bootblock_common.h> #include <bootblock_common.h>
#include <device/pci_ops.h>
#include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/i82801gx/i82801gx.h>
#include <northbridge/intel/pineview/pineview.h> #include <northbridge/intel/pineview/pineview.h>
#include <superio/ite/common/ite.h> #include <superio/ite/common/ite.h>

1
src/mainboard/gigabyte/ga-b75m-d3h/early_init.c
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@ -14,7 +14,6 @@
*/ */
#include <bootblock_common.h> #include <bootblock_common.h>
#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>

1
src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c
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@ -14,7 +14,6 @@
*/ */
#include <bootblock_common.h> #include <bootblock_common.h>
#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>

2
src/mainboard/google/butterfly/early_init.c
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@ -15,8 +15,6 @@
*/ */
#include <stdint.h> #include <stdint.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>

2
src/mainboard/google/parrot/early_init.c
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@ -15,8 +15,6 @@
*/ */
#include <stdint.h> #include <stdint.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>

2
src/mainboard/google/stout/early_init.c
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@ -15,8 +15,6 @@
*/ */
#include <stdint.h> #include <stdint.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <console/console.h> #include <console/console.h>

1
src/mainboard/hp/2570p/early_init.c
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@ -15,7 +15,6 @@
*/ */
#include <bootblock_common.h> #include <bootblock_common.h>
#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>

1
src/mainboard/hp/2760p/early_init.c
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@ -14,7 +14,6 @@
*/ */
#include <bootblock_common.h> #include <bootblock_common.h>
#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>

1
src/mainboard/hp/8460p/early_init.c
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@ -15,7 +15,6 @@
*/ */
#include <bootblock_common.h> #include <bootblock_common.h>
#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>

1
src/mainboard/hp/8470p/early_init.c
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@ -14,7 +14,6 @@
*/ */
#include <bootblock_common.h> #include <bootblock_common.h>
#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>

1
src/mainboard/hp/8770w/early_init.c
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@ -15,7 +15,6 @@
*/ */
#include <bootblock_common.h> #include <bootblock_common.h>
#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>

2
src/mainboard/hp/compaq_8200_elite_sff/early_init.c
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@ -18,8 +18,6 @@
#include <bootblock_common.h> #include <bootblock_common.h>
#include <stdint.h> #include <stdint.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <superio/nuvoton/npcd378/npcd378.h> #include <superio/nuvoton/npcd378/npcd378.h>
#include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/common/nuvoton.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>

1
src/mainboard/hp/folio_9470m/early_init.c
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@ -16,7 +16,6 @@
*/ */
#include <bootblock_common.h> #include <bootblock_common.h>
#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>

1
src/mainboard/hp/revolve_810_g1/early_init.c
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@ -19,7 +19,6 @@
#include <string.h> #include <string.h>
#include <cbfs.h> #include <cbfs.h>
#include <console/console.h> #include <console/console.h>
#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>

2
src/mainboard/hp/z220_sff_workstation/early_init.c
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@ -18,8 +18,6 @@
#include <bootblock_common.h> #include <bootblock_common.h>
#include <stdint.h> #include <stdint.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <superio/nuvoton/npcd378/npcd378.h> #include <superio/nuvoton/npcd378/npcd378.h>
#include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/common/nuvoton.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>

2
src/mainboard/intel/dcp847ske/early_southbridge.c
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@ -19,8 +19,6 @@
#include <bootblock_common.h> #include <bootblock_common.h>
#include <stdint.h> #include <stdint.h>
#include <cf9_reset.h> #include <cf9_reset.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <console/console.h> #include <console/console.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>

2
src/mainboard/intel/emeraldlake2/early_init.c
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@ -17,8 +17,6 @@
#include <bootblock_common.h> #include <bootblock_common.h>
#include <stdint.h> #include <stdint.h>
#include <arch/io.h> #include <arch/io.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <superio/smsc/sio1007/sio1007.h> #include <superio/smsc/sio1007/sio1007.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>

2
src/mainboard/lenovo/l520/early_init.c
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@ -15,8 +15,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>

2
src/mainboard/lenovo/x131e/early_init.c
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@ -15,8 +15,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>

2
src/mainboard/lenovo/x1_carbon_gen1/early_init.c
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@ -18,8 +18,6 @@
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <console/console.h> #include <console/console.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>

2
src/mainboard/lenovo/x220/early_init.c
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@ -16,8 +16,6 @@
*/ */
#include <stdint.h> #include <stdint.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>

2
src/mainboard/lenovo/x230/early_init.c
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@ -16,8 +16,6 @@
*/ */
#include <stdint.h> #include <stdint.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>

1
src/mainboard/roda/rv11/variants/rv11/early_init.c
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@ -15,7 +15,6 @@
#include <stdint.h> #include <stdint.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>

1
src/mainboard/roda/rv11/variants/rw11/early_init.c
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@ -16,7 +16,6 @@
#include <bootblock_common.h> #include <bootblock_common.h>
#include <stdint.h> #include <stdint.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
#include <device/pnp.h> #include <device/pnp.h>
#include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit.h>

2
src/mainboard/samsung/lumpy/early_init.c
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@ -18,8 +18,6 @@
#include <string.h> #include <string.h>
#include <arch/io.h> #include <arch/io.h>
#include <bootblock_common.h> #include <bootblock_common.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <cbfs.h> #include <cbfs.h>
#include <console/console.h> #include <console/console.h>

2
src/mainboard/samsung/stumpy/early_init.c
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@ -16,8 +16,6 @@
#include <bootblock_common.h> #include <bootblock_common.h>
#include <stdint.h> #include <stdint.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <console/console.h> #include <console/console.h>