diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb
index c78189f9a5..544f9e251b 100644
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb
@@ -95,9 +95,9 @@ chip soc/intel/alderlake
 			}"
 			chip soc/intel/common/block/pcie/rtd3
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)"
-				register "enable_delay_ms" = "50"
+				register "enable_delay_ms" = "100"
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)"
-				register "reset_off_delay_ms" = "20"
+				register "reset_delay_ms" = "20"
 				register "srcclk_pin" = "7"
 				device generic 0 on
 				end
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb
index c78189f9a5..544f9e251b 100644
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb
@@ -95,9 +95,9 @@ chip soc/intel/alderlake
 			}"
 			chip soc/intel/common/block/pcie/rtd3
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)"
-				register "enable_delay_ms" = "50"
+				register "enable_delay_ms" = "100"
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)"
-				register "reset_off_delay_ms" = "20"
+				register "reset_delay_ms" = "20"
 				register "srcclk_pin" = "7"
 				device generic 0 on
 				end