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mb/intel/{saddlebrook,kunimitsu}: Add macro for SaGv config

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Change-Id: Ia31da9997ba46c15cd385bf55e009cf299848b64
Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36423
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Praveen Hodagatta Pranesh 2019-10-29 14:47:11 +08:00 committed by Patrick Georgi
parent b7731574f4
commit aa6a8fb919
2 changed files with 2 additions and 2 deletions
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2
src/mainboard/intel/kunimitsu/devicetree.cb
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@ -34,7 +34,7 @@ chip soc/intel/skylake
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"
register "SaGv" = "SaGv_Enabled"
register "PmTimerDisabled" = "1"
register "pirqa_routing" = "PCH_IRQ11"

2
src/mainboard/intel/saddlebrook/devicetree.cb
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@ -42,7 +42,7 @@ chip soc/intel/skylake
register "Device4Enable" = "0"
register "Heci3Enabled" = "0"
register "SaGv" = "3"
register "SaGv" = "SaGv_Enabled"
register "PmTimerDisabled" = "0"
# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch