drop unused files
drop some non-car code from amd/dualcore (there is no AMD dualcore without CAR) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
0e34aeffd3
commit
aa987b23e4
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@ -1,17 +0,0 @@
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/*
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* init sections to place code running with cache as ram.
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*
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* 2004 by Stefan Reinauer <stepan@openbios.org>
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*/
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SECTIONS {
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.init . : {
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_init = .;
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*(.init.text);
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*(.init.rodata);
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*(.init.rodata.*);
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. = ALIGN(16);
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_einit = .;
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}
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}
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@ -1,6 +1,7 @@
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/* 2005.6 by yhlu
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/* 2005.6 by yhlu
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* 2006.3 yhlu add copy data from CAR to ram
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* 2006.3 yhlu add copy data from CAR to ram
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*/
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*/
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#include <arch/stages.h>
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#include "cpu/amd/car/disable_cache_as_ram.c"
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#include "cpu/amd/car/disable_cache_as_ram.c"
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static inline void print_debug_pcar(const char *strval, uint32_t val)
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static inline void print_debug_pcar(const char *strval, uint32_t val)
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@ -70,95 +70,5 @@ static inline void start_other_cores(void)
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}
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}
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}
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}
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#if CONFIG_USE_DCACHE_RAM == 0
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static void do_k8_init_and_stop_secondaries(void)
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{
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struct node_core_id id;
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device_t dev;
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unsigned apicid;
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unsigned max_siblings;
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msr_t msr;
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/* Skip this if there was a built in self test failure */
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if (is_cpu_pre_e0()) {
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id.nodeid = lapicid() & 0x7;
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id.coreid = 0;
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} else {
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/* Which cpu are we on? */
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id = get_node_core_id_x();
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/* Set NB_CFG_MSR
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* Linux expect the core to be in the least signficant bits.
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*/
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msr = rdmsr(NB_CFG_MSR);
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msr.hi |= (1<<(54-32)); // InitApicIdCpuIdLo
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wrmsr(NB_CFG_MSR, msr);
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}
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/* For now assume all cpus have the same number of siblings */
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max_siblings = (cpuid_ecx(0x80000008) & 0xff) + 1;
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/* Enable extended apic ids */
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device_t dev_f0 = PCI_DEV(0, 0x18+id.nodeid, 0);
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unsigned val = pci_read_config32(dev_f0, 0x68);
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val |= (1 << 18) | (1 << 17);
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pci_write_config32(dev_f0, 0x68, val);
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/* Set the lapicid */
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#if (CONFIG_ENABLE_APIC_EXT_ID == 1)
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unsigned initial_apicid = get_initial_apicid();
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#if CONFIG_LIFT_BSP_APIC_ID == 0
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if( initial_apicid != 0 ) // other than bsp
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#endif
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{
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/* use initial apic id to lift it */
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uint32_t dword = lapic_read(LAPIC_ID);
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dword &= ~(0xff<<24);
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dword |= (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff)<<24);
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lapic_write(LAPIC_ID, dword);
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}
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#if CONFIG_LIFT_BSP_APIC_ID == 1
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bsp_apicid += CONFIG_APIC_ID_OFFSET;
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#endif
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#endif
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/* Remember the cpuid */
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if (id.coreid == 0) {
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dev = PCI_DEV(0, 0x18 + id.nodeid, 2);
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pci_write_config32(dev, 0x9c, cpuid_eax(1));
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}
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/* Maybe call distinguish_cpu_resets only on the last core? */
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distinguish_cpu_resets(id.nodeid);
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if (!boot_cpu()) {
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stop_this_cpu();
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}
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}
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static void k8_init_and_stop_secondaries(void)
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{
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/* This doesn't work with Cache As Ram because it messes with
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the MTRR state, which breaks the init detection.
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do_k8_init_and_stop_secondaries should be usable by CAR code.
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*/
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int init_detected;
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init_detected = early_mtrr_init_detected();
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amd_early_mtrr_init();
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enable_lapic();
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init_timer();
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if (init_detected) {
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asm volatile ("jmp __cpu_reset");
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}
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do_k8_init_and_stop_secondaries();
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}
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#endif
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@ -1,2 +1 @@
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gdtptr16_offset = gdtptr16 & 0xffff;
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gdtptr16_offset = gdtptr16 & 0xffff;
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_start_offset = _start & 0xffff;
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@ -1,10 +0,0 @@
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.section ".reset"
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.code16
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.globl reset_vector
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reset_vector:
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. = 0x8;
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.code32
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jmp protected_start
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.previous
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@ -1,14 +0,0 @@
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/*
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* _ROMTOP : The top of the rom used where we
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* need to put the reset vector.
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*/
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SECTIONS {
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_ROMTOP = CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10;
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. = _ROMTOP;
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.reset (.): {
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*(.reset)
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. = 15 ;
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BYTE(0x00);
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}
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}
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@ -1,3 +1,23 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2004 Stefan Reinauer
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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SECTIONS {
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SECTIONS {
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.init . : {
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.init . : {
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_init = .;
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_init = .;
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@ -7,5 +27,4 @@ SECTIONS {
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. = ALIGN(16);
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. = ALIGN(16);
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_einit = .;
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_einit = .;
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}
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}
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}
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}
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