GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

sb/intel/i82801jx: Move early sb init to a common place 

Setting southbridge GPIO is now done after console init,
which should be fine. This code is partially copied from
i82801ix.

Change-Id: I51dd30de4a82898b0f1d8c4308e8de4a00d1b7aa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36756
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2019-11-11 20:08:12 +01:00 committed by Patrick Georgi
parent 399b6c11ef
commit aa990e9289
6 changed files with 81 additions and 53 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
src/mainboard/asus/p5qc/romstage.c
View File

@ -17,7 +17,6 @@
#include <device/pci_ops.h>
#include <console/console.h>
#include <southbridge/intel/i82801jx/i82801jx.h>
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/common/pmclib.h>
#include <northbridge/intel/x4x/x4x.h>
#include <arch/romstage.h>
@ -31,20 +30,8 @@
* We should use standard gpio.h eventually
*/
static void mb_gpio_init(void)
static void mb_misc_rcba(void)
{
/* Set the value for GPIO base address register and enable GPIO. */
pci_write_config32(LPC_DEV, D31F0_GPIO_BASE, (DEFAULT_GPIOBASE | 1));
pci_write_config8(LPC_DEV, D31F0_GPIO_CNTL, 0x10);
setup_pch_gpios(&mainboard_gpio_map);
/* Set default GPIOs on superio: TODO (here or in ramstage) */
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
RCBA8(0x31ff);
/* TODO? */
RCBA32(RCBA_CG) = 0xbf7f001f;
RCBA32(0x3430) = 0x00000002;
@ -59,13 +46,14 @@ void mainboard_romstage_entry(void)
/* Set southbridge and Super I/O GPIOs. */
i82801jx_lpc_setup();
mb_gpio_init();
mb_misc_rcba();
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
enable_smbus();
i82801jx_early_init();
x4x_early_init();
s3_resume = southbridge_detect_s3_resume();

16
src/mainboard/asus/p5ql-em/romstage.c
View File

@ -16,7 +16,6 @@
#include <device/pnp_ops.h>
#include <console/console.h>
#include <southbridge/intel/i82801jx/i82801jx.h>
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/common/pmclib.h>
#include <northbridge/intel/x4x/x4x.h>
#include <cpu/x86/msr.h>
@ -104,19 +103,6 @@ static int setup_sio_gpio(void)
return need_reset;
}
static void mb_gpio_init(void)
{
/* Set the value for GPIO base address register and enable GPIO. */
pci_write_config32(LPC_DEV, D31F0_GPIO_BASE, (DEFAULT_GPIOBASE | 1));
pci_write_config8(LPC_DEV, D31F0_GPIO_CNTL, 0x10);
setup_pch_gpios(&mainboard_gpio_map);
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
RCBA8(0x31ff);
}
void mainboard_romstage_entry(void)
{
/* This board has first dimm slot of each channel hooked up to
@ -129,13 +115,13 @@ void mainboard_romstage_entry(void)
/* Set southbridge and Super I/O GPIOs. */
i82801jx_lpc_setup();
mb_gpio_init();
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
enable_smbus();
i82801jx_early_init();
x4x_early_init();
s3_resume = southbridge_detect_s3_resume();

18
src/mainboard/intel/dg43gt/romstage.c
View File

@ -17,7 +17,6 @@
#include <device/pci_ops.h>
#include <console/console.h>
#include <southbridge/intel/i82801jx/i82801jx.h>
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/common/pmclib.h>
#include <northbridge/intel/x4x/x4x.h>
#include <arch/romstage.h>
@ -31,20 +30,8 @@
* We should use standard gpio.h eventually
*/
static void mb_gpio_init(void)
static void mb_misc_rcba(void)
{
/* Set the value for GPIO base address register and enable GPIO. */
pci_write_config32(LPC_DEV, D31F0_GPIO_BASE, (DEFAULT_GPIOBASE | 1));
pci_write_config8(LPC_DEV, D31F0_GPIO_CNTL, 0x10);
setup_pch_gpios(&mainboard_gpio_map);
/* Set default GPIOs on superio: TODO (here or in ramstage) */
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
RCBA8(0x31ff);
RCBA32(0x3410) = 0x00060464;
RCBA32(RCBA_BUC) &= ~BUC_LAND;
RCBA32(0x3418) = 0x01320001;
@ -61,13 +48,14 @@ void mainboard_romstage_entry(void)
/* Set southbridge and Super I/O GPIOs. */
i82801jx_lpc_setup();
mb_gpio_init();
mb_misc_rcba();
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
enable_smbus();
i82801jx_early_init();
x4x_early_init();
s3_resume = southbridge_detect_s3_resume();

4
src/northbridge/intel/x4x/early_init.c
View File

@ -42,8 +42,10 @@ void x4x_early_init(void)
pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1);
/* Setup PMBASE */
if (!CONFIG(SOUTHBRIDGE_INTEL_I82801JX)) {
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x80);
}
/* Setup HECIBAR */
pci_write_config32(PCI_DEV(0, 3, 0), 0x10, DEFAULT_HECIBAR);
@ -57,12 +59,14 @@ void x4x_early_init(void)
pci_write_config8(d0f0, D0F0_PAM(5), 0x33);
pci_write_config8(d0f0, D0F0_PAM(6), 0x33);
if (!CONFIG(SOUTHBRIDGE_INTEL_I82801JX)) {
printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
outw(1 << 11, DEFAULT_PMBASE + 0x60 + 0x08); /* halt timer */
outw(1 << 3, DEFAULT_PMBASE + 0x60 + 0x04); /* clear timeout */
outw(1 << 1, DEFAULT_PMBASE + 0x60 + 0x06); /* clear 2nd timeout */
printk(BIOS_DEBUG, " done.\n");
}
if (!(pci_read_config32(d0f0, D0F0_CAPID0 + 4) & (1 << (46 - 32)))) {
/* Enable internal GFX */

61
src/southbridge/intel/i82801jx/early_init.c
View File

@ -12,7 +12,10 @@
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <device/pci_ops.h>
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/common/pmbase.h>
#include "i82801jx.h"
#include "chip.h"
@ -52,3 +55,61 @@ void i82801jx_lpc_setup(void)
pci_write_config32(d31f0, D31F0_GEN3_DEC, config->gen3_dec);
pci_write_config32(d31f0, D31F0_GEN4_DEC, config->gen4_dec);
}
static void i82801jx_setup_bars(void)
{
const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
/* Set up RCBA. */
pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
/* Set up PMBASE. */
pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1);
/* Enable PMBASE. */
pci_write_config8(d31f0, D31F0_ACPI_CNTL, 0x80);
/* Set up GPIOBASE. */
pci_write_config32(d31f0, D31F0_GPIO_BASE, DEFAULT_GPIOBASE);
/* Enable GPIO. */
pci_write_config8(d31f0, D31F0_GPIO_CNTL,
pci_read_config8(d31f0, D31F0_GPIO_CNTL) | 0x10);
}
#define TCO_BASE 0x60
void i82801jx_early_init(void)
{
const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
printk(BIOS_DEBUG, "Setting up static southbridge registers...");
i82801jx_setup_bars();
printk(BIOS_DEBUG, " done.\n");
setup_pch_gpios(&mainboard_gpio_map);
printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
write_pmbase16(TCO_BASE + 0x8, (1 << 11)); /* halt timer */
write_pmbase16(TCO_BASE + 0x4, (1 << 3)); /* clear timeout */
write_pmbase16(TCO_BASE + 0x6, (1 << 1)); /* clear 2nd timeout */
printk(BIOS_DEBUG, " done.\n");
/* Enable IOAPIC */
RCBA8(OIC) = 0x3;
RCBA8(OIC);
/* Initialize power management initialization
register early as it affects reboot behavior. */
/* Bit 20 activates global reset of host and ME on cf9 writes of 0x6
and 0xe (required if ME is disabled but present), bit 31 locks it.
The other bits are 'must write'. */
u8 reg8 = pci_read_config8(d31f0, 0xac);
reg8 |= (1 << 31) | (1 << 30) | (1 << 20) | (3 << 8);
pci_write_config8(d31f0, 0xac, reg8);
/* TODO: If RTC power failed, reset RTC state machine
(set, then reset RTC 0x0b bit7) */
/* TODO: Check power state bits in GEN_PMCON_2 (D31F0 0xa2)
before they get cleared. */
}

1
src/southbridge/intel/i82801jx/i82801jx.h
View File

@ -235,6 +235,7 @@ int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
const u8 *buf);
#endif
void i82801jx_lpc_setup(void);
void i82801jx_early_init(void);
#endif