superio/winbond/*: Unify w*_set_clksel_48()

This function is identical throughout all Winbond superios in
the tree, so move it into superio/winbond/common/early_init.c,
renamed from early_serial.c because it now does more than just
early serial.

Change all affected mainboards to use the unified function.

Change-Id: If05e0db93375641917e538d83aacd1b50fbd033b
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/mainboard/advansus/a785e-i/romstage.c

@@ -100,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	enable_rs780_dev8();
 	sb800_clk_output_48Mhz();
 
-	w83627hf_set_clksel_48(PNP_DEV(0x2e, 0));
+	winbond_set_clksel_48(PNP_DEV(0x2e, 0));
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
 	console_init();

src/mainboard/avalue/eax-785e/romstage.c

@@ -100,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	enable_rs780_dev8();
 	sb800_clk_output_48Mhz();
 
-	w83627hf_set_clksel_48(CLK_DEV);
+	winbond_set_clksel_48(CLK_DEV);
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
 	console_init();

src/mainboard/bcom/winnetp680/romstage.c

@@ -78,7 +78,7 @@ void main(unsigned long bist)
 	/* Enable multifunction for northbridge. */
 	pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
 
-	w83697hf_set_clksel_48(SERIAL_DEV);
+	winbond_set_clksel_48(SERIAL_DEV);
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 

src/mainboard/msi/ms6178/romstage.c

@@ -33,7 +33,7 @@
 
 void mainboard_romstage_entry(unsigned long bist)
 {
-	w83627hf_set_clksel_48(DUMMY_DEV);
+	winbond_set_clksel_48(DUMMY_DEV);
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
 	console_init();

src/mainboard/supermicro/h8dme/romstage.c

@@ -140,7 +140,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 
-	w83627hf_set_clksel_48(DUMMY_DEV);
+	winbond_set_clksel_48(DUMMY_DEV);
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
 	console_init();

src/mainboard/supermicro/h8dmr/romstage.c

@@ -120,7 +120,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 
-	w83627hf_set_clksel_48(DUMMY_DEV);
+	winbond_set_clksel_48(DUMMY_DEV);
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
 	console_init();

src/mainboard/supermicro/h8dmr_fam10/romstage.c

@@ -130,7 +130,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x32);
 
-	w83627hf_set_clksel_48(DUMMY_DEV);
+	winbond_set_clksel_48(DUMMY_DEV);
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
 	console_init();

src/mainboard/supermicro/h8qme_fam10/romstage.c

@@ -195,7 +195,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x32);
 
-	w83627hf_set_clksel_48(DUMMY_DEV);
+	winbond_set_clksel_48(DUMMY_DEV);
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
 	console_init();

src/mainboard/tyan/s8226/romstage.c

@@ -53,7 +53,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	report_bist_failure(bist);
 
 	sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */
-	w83627dhg_set_clksel_48(DUMMY_DEV);
+	winbond_set_clksel_48(DUMMY_DEV);
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	sb7xx_51xx_disable_wideio(0);
 	post_code(0x34);

src/mainboard/via/epia-m700/romstage.c

@@ -378,7 +378,7 @@ void main(unsigned long bist)
 	 */
 	pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01);
 	/* EmbedComInit(); */
-	w83697hf_set_clksel_48(DUMMY_DEV);
+	winbond_set_clksel_48(DUMMY_DEV);
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	/* enable_vx800_serial(); */
 

src/mainboard/winent/pl6064/romstage.c

@@ -59,7 +59,7 @@ void asmlinkage mainboard_romstage_entry(unsigned long bist)
 	/* Note: must do this AFTER the early_setup! It is counting on some
 	 * early MSR setup for CS5536.
 	 */
-	w83627hf_set_clksel_48(SERIAL_DEV);
+	winbond_set_clksel_48(SERIAL_DEV);
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 

src/mainboard/winnet/g170/romstage.c

@@ -78,7 +78,7 @@ void main(unsigned long bist)
 	/* Enable multifunction for northbridge. */
 	pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
 
-	w83697hf_set_clksel_48(SERIAL_DEV);
+	winbond_set_clksel_48(SERIAL_DEV);
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 

src/superio/winbond/Makefile.inc

@@ -14,7 +14,7 @@
 ##
 
 ## include generic winbond pre-ram stage driver
-romstage-$(CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE) += common/early_serial.c
+romstage-$(CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE) += common/early_init.c
 
 subdirs-y += w83627dhg
 subdirs-y += w83627ehg

src/superio/winbond/common/early_init.c

@@ -15,7 +15,7 @@
  */
 
 /*
- * A generic romstage (pre-ram) driver for Winbond variant Super I/O chips.
+ * A generic romstage (pre-ram) driver for various Winbond Super I/O chips.
  *
  * The following is derived directly from the vendor Winbond's data-sheets:
  *
@@ -79,3 +79,14 @@ void winbond_set_pinmux(pnp_devfn_t dev, uint8_t offset, uint8_t mask, uint8_t s
 	pnp_write_config(dev, offset, byte);
 	pnp_exit_conf_state(dev);
 }
+
+void winbond_set_clksel_48(pnp_devfn_t dev)
+{
+	u8 reg8;
+
+	pnp_enter_conf_state(dev);
+	reg8 = pnp_read_config(dev, 0x24);
+	reg8 |= (1 << 6); /* Set the clock input to 48MHz. */
+	pnp_write_config(dev, 0x24, reg8);
+	pnp_exit_conf_state(dev);
+}

src/superio/winbond/common/winbond.h

@@ -22,6 +22,7 @@
 
 void winbond_enable_serial(pnp_devfn_t dev, uint16_t iobase);
 void winbond_set_pinmux(pnp_devfn_t dev, uint8_t offset, uint8_t mask, uint8_t state);
+void winbond_set_clksel_48(pnp_devfn_t dev);
 
 void pnp_enter_conf_state(pnp_devfn_t dev);
 void pnp_exit_conf_state(pnp_devfn_t dev);