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soc/intel/elkhartlake: Update SA & PM related definitions 

1. Update SA base address & size
2. Update GBE control bit register value

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I1f5036c9cd75682fcf239170bcb257ffaa002e7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Tan, Lean Sheng 2020-09-03 07:08:53 -07:00 committed by Patrick Georgi
parent b369dde9b1
commit aab188174f
2 changed files with 3 additions and 3 deletions
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4
src/soc/intel/elkhartlake/include/soc/iomap.h
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@ -47,8 +47,8 @@
#define VTD_BASE_ADDRESS 0xfed90000
#define VTD_BASE_SIZE 0x00004000
#define MCH_BASE_ADDRESS 0xfea80000
#define MCH_BASE_SIZE 0x8000
#define MCH_BASE_ADDRESS 0xfec80000
#define MCH_BASE_SIZE 0x80000
#define EARLY_GSPI_BASE_ADDRESS 0xfe011000

2
src/soc/intel/elkhartlake/include/soc/pm.h
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@ -65,7 +65,7 @@
#define SMI_ON_SLP_EN_STS_BIT 4
#define LEGACY_USB_STS_BIT 3
#define BIOS_STS_BIT 2
#define GPE_CNTL 0x42
#define GPE_CNTL 0x40
#define SWGPE_CTRL (1 << 1)
#define DEVACT_STS 0x44
#define PM2_CNT 0x50