cpu/amd/family_10h-family_15h: Set up cache controls on Family 15h to improve performance
Change-Id: I3df571d8091c07ac1ee29bf16b5a68585fa9eed4 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12039 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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@ -135,8 +135,9 @@ static const struct {
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0x00000000, 1 << (42-32)}, /* Bx [PwcDisableWalkerSharing]=1 */
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0x00000000, 1 << (42-32)}, /* Bx [PwcDisableWalkerSharing]=1 */
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{ BU_CFG3, AMD_OR_C0, AMD_PTYPE_ALL,
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{ BU_CFG3, AMD_OR_C0, AMD_PTYPE_ALL,
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1 << 22, 0x00000000,
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(0x3 << 20) | (0x1 << 22), 0x00000000,
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1 << 22, 0x00000000}, /* C0 or above [PfcDoubleStride]=1 */
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(0x3 << 20) | (0x1 << 22), 0x00000000}, /* C0 or above [PfcDoubleStride]=1,
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PfcStrideMul]=0x3 */
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{ EX_CFG, AMD_OR_C0, AMD_PTYPE_ALL,
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{ EX_CFG, AMD_OR_C0, AMD_PTYPE_ALL,
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0x00000000, 1 << (54-32),
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0x00000000, 1 << (54-32),
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@ -629,6 +630,11 @@ static const struct {
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* System software should set F5x88[14] to 1b. */
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* System software should set F5x88[14] to 1b. */
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{ 5, 0x88, AMD_OR_B2, AMD_PTYPE_ALL,
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{ 5, 0x88, AMD_OR_B2, AMD_PTYPE_ALL,
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1 << 14, 1 << 14 },
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1 << 14, 1 << 14 },
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/* L3 Control 2 */
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{ 3, 0x1b8, AMD_FAM15_ALL, AMD_PTYPE_ALL,
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0x00000090, 0x000001d0 }, /* ImplRdProjDelayThresh = 0x2,
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ImplRdAnySubUnavail = 0x1 */
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};
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};
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