emulation/x86 : Drop HAVE_ACPI_RESUME

S3 resume detection not implemented in romstage.c.

Change-Id: I98277cb483825af2e6c5c8eefa4598b117613478
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6028
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Kyösti Mälkki 2014-06-15 12:00:08 +03:00
parent a1e924ca6b
commit aac45febc7
3 changed files with 0 additions and 23 deletions

View File

@ -8,7 +8,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
select BOARD_ROMSIZE_KB_256
select EARLY_CBMEM_INIT
select MAINBOARD_HAS_NATIVE_VGA_INIT

View File

@ -59,27 +59,6 @@ before_romstage:
post_code(0x30)
#if CONFIG_HAVE_ACPI_RESUME
movl CBMEM_BOOT_MODE, %eax
cmpl $0x2, %eax // Resume?
jne __acpi_resume_backup_done
/* copy 1MB - 64K to high tables ram_base to prevent memory corruption
* through stage 2. We could keep stuff like stack and heap in high
* tables memory completely, but that's a wonderful clean up task for
* another day.
*/
cld
movl $CONFIG_RAMBASE, %esi
movl CBMEM_RESUME_BACKUP, %edi
movl $HIGH_MEMORY_SAVE / 4, %ecx
rep movsl
__acpi_resume_backup_done:
#endif
post_code(0x3d)
__main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */

View File

@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
# select HAVE_OPTION_TABLE
# select HAVE_PIRQ_TABLE
select HAVE_ACPI_TABLES
# select HAVE_ACPI_RESUME
select BOARD_ROMSIZE_KB_256
select EARLY_CBMEM_INIT
select MAINBOARD_HAS_NATIVE_VGA_INIT