cpu/intel/common: Use a common acpi/cpu.asl file

Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: David Guckian
This commit is contained in:
Arthur Heymans 2018-11-28 13:53:15 +01:00 committed by Duncan Laurie
parent cf9fc1ddfe
commit aaced4a932
93 changed files with 81 additions and 473 deletions

View File

@ -1,36 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* These come from the dynamically created CPU SSDT */
External (\_PR.CNOT, MethodObj)
/* Notify OS to re-read CPU tables */
Method (PNOT)
{
\_PR.CNOT (0x81)
}
/* Notify OS to re-read CPU _PPC limit */
Method (PPCN)
{
\_PR.CNOT (0x80)
}
/* Notify OS to re-read Throttle Limit tables */
Method (TNOT)
{
\_PR.CNOT (0x82)
}

View File

@ -1,36 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* These come from the dynamically created CPU SSDT */
External (\_PR.CNOT, MethodObj)
/* Notify OS to re-read CPU tables */
Method (PNOT)
{
\_PR.CNOT (0x81)
}
/* Notify OS to re-read CPU _PPC limit */
Method (PPCN)
{
\_PR.CNOT (0x80)
}
/* Notify OS to re-read Throttle Limit tables */
Method (TNOT)
{
\_PR.CNOT (0x82)
}

View File

@ -38,7 +38,7 @@ DefinitionBlock(
#include "acpi/thermal.asl"
#include <cpu/intel/fsp_model_406dx/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -26,7 +26,7 @@ DefinitionBlock(
{
// Some generic macros
#include "acpi/platform.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>

View File

@ -29,7 +29,7 @@ DefinitionBlock(
{
// Some generic macros
#include "acpi/platform.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>

View File

@ -28,7 +28,7 @@ DefinitionBlock(
#include <southbridge/intel/lynxpoint/acpi/platform.asl>
#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
#include <southbridge/intel/lynxpoint/acpi/sleepstates.asl>
#include <cpu/intel/haswell/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB)
{

View File

@ -25,7 +25,7 @@ DefinitionBlock(
)
{
#include "acpi/platform.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>

View File

@ -25,7 +25,7 @@ DefinitionBlock(
)
{
#include "acpi/platform.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>

View File

@ -27,7 +27,7 @@ DefinitionBlock(
// Some generic macros
#include "acpi/platform.asl"
#include "acpi/superio.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
/* global NVS and variables. */

View File

@ -29,7 +29,7 @@ DefinitionBlock(
{
// Some generic macros
#include "acpi/platform.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>

View File

@ -38,7 +38,7 @@ DefinitionBlock(
// global NVS and variables
#include <soc/intel/fsp_baytrail/acpi/globalnvs.asl>
#include <soc/intel/fsp_baytrail/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -25,7 +25,7 @@ DefinitionBlock(
// Some generic macros
#include "acpi/platform.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>

View File

@ -25,7 +25,7 @@ DefinitionBlock(
// Some generic macros
#include "acpi/platform.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>

View File

@ -29,7 +29,7 @@ DefinitionBlock(
#include "acpi/platform.asl"
#include "acpi/superio.asl"
#include "acpi/thermal.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
/* global NVS and variables. */

View File

@ -37,7 +37,7 @@ DefinitionBlock(
//#include "acpi/gpe.asl"
// CPU
#include <soc/intel/broadwell/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -34,7 +34,7 @@ DefinitionBlock(
#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
// CPU
#include <cpu/intel/haswell/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -39,7 +39,7 @@ DefinitionBlock(
// General Purpose Events
//#include "acpi/gpe.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -31,7 +31,7 @@ DefinitionBlock(
/* global NVS and variables */
#include <acpi/globalnvs.asl>
#include <acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -33,7 +33,7 @@ DefinitionBlock(
#include <soc/intel/icelake/acpi/globalnvs.asl>
// CPU
#include <soc/intel/icelake/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -33,7 +33,7 @@ DefinitionBlock(
#include <soc/intel/skylake/acpi/globalnvs.asl>
/* CPU */
#include <soc/intel/skylake/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB)
{

View File

@ -33,7 +33,7 @@ DefinitionBlock(
#include <soc/intel/skylake/acpi/globalnvs.asl>
/* CPU */
#include <soc/intel/skylake/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB)
{

View File

@ -32,7 +32,7 @@ DefinitionBlock(
#include <soc/intel/skylake/acpi/globalnvs.asl>
// CPU
#include <soc/intel/skylake/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -37,7 +37,7 @@ DefinitionBlock(
//#include "acpi/gpe.asl"
// CPU
#include <soc/intel/broadwell/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -40,7 +40,7 @@ DefinitionBlock(
//#include "acpi/gpe.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -30,7 +30,7 @@ DefinitionBlock(
#include <soc/intel/apollolake/acpi/globalnvs.asl>
/* CPU */
#include <soc/intel/apollolake/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -38,7 +38,7 @@ DefinitionBlock(
// General Purpose Events
//#include "acpi/gpe.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -33,7 +33,7 @@ DefinitionBlock(
#include <soc/intel/skylake/acpi/globalnvs.asl>
/* CPU */
#include <soc/intel/skylake/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB)
{

View File

@ -32,7 +32,7 @@ DefinitionBlock(
// global NVS and variables
#include <soc/intel/baytrail/acpi/globalnvs.asl>
#include <soc/intel/baytrail/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -30,7 +30,7 @@ DefinitionBlock(
#include <soc/intel/apollolake/acpi/globalnvs.asl>
/* CPU */
#include <soc/intel/apollolake/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -32,7 +32,7 @@ DefinitionBlock(
#include <soc/intel/cannonlake/acpi/globalnvs.asl>
/* CPU */
#include <soc/intel/cannonlake/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PWRB)

View File

@ -37,7 +37,7 @@ DefinitionBlock(
//#include "acpi/gpe.asl"
// CPU
#include <cpu/intel/haswell/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -40,7 +40,7 @@ DefinitionBlock(
// General Purpose Events
//#include "acpi/gpe.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -35,7 +35,7 @@ DefinitionBlock(
#include <soc/intel/cannonlake/acpi/globalnvs.asl>
// CPU
#include <soc/intel/cannonlake/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -28,7 +28,7 @@ DefinitionBlock(
{
// Some generic macros
#include "acpi/platform.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>

View File

@ -28,7 +28,7 @@ DefinitionBlock(
{
// Some generic macros
#include "acpi/platform.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>

View File

@ -28,7 +28,7 @@ DefinitionBlock(
{
// Some generic macros
#include "acpi/platform.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>

View File

@ -28,7 +28,7 @@ DefinitionBlock(
{
// Some generic macros
#include "acpi/platform.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>

View File

@ -28,7 +28,7 @@ DefinitionBlock(
{
// Some generic macros
#include "acpi/platform.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>

View File

@ -28,7 +28,7 @@ DefinitionBlock(
{
// Some generic macros
#include "acpi/platform.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>

View File

@ -28,7 +28,7 @@ DefinitionBlock(
{
// Some generic macros
#include "acpi/platform.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>

View File

@ -28,7 +28,7 @@ DefinitionBlock(
{
// Some generic macros
#include "acpi/platform.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>

View File

@ -37,7 +37,7 @@ DefinitionBlock(
#include "acpi/thermal.asl"
#include <cpu/intel/haswell/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -38,7 +38,7 @@ DefinitionBlock(
// global NVS and variables
#include <soc/intel/fsp_baytrail/acpi/globalnvs.asl>
#include <soc/intel/fsp_baytrail/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -26,7 +26,7 @@ DefinitionBlock(
{
// Some generic macros
#include "acpi/platform.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>

View File

@ -38,7 +38,7 @@ DefinitionBlock(
// General Purpose Events
//#include "acpi/gpe.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -30,7 +30,7 @@ DefinitionBlock(
#include <soc/intel/apollolake/acpi/globalnvs.asl>
/* CPU */
#include <soc/intel/apollolake/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -39,7 +39,7 @@ DefinitionBlock(
// global NVS and variables
#include <soc/intel/denverton_ns/acpi/globalnvs.asl>
#include <soc/intel/denverton_ns/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -33,7 +33,7 @@ DefinitionBlock(
#include <soc/intel/icelake/acpi/globalnvs.asl>
// CPU
#include <soc/intel/icelake/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -32,7 +32,7 @@ DefinitionBlock(
#include <soc/intel/skylake/acpi/globalnvs.asl>
// CPU
#include <soc/intel/skylake/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -32,7 +32,7 @@ DefinitionBlock(
#include <soc/intel/skylake/acpi/globalnvs.asl>
// CPU
#include <soc/intel/skylake/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -27,7 +27,7 @@ DefinitionBlock(
#include <soc/intel/apollolake/acpi/globalnvs.asl>
/* CPU */
#include <soc/intel/apollolake/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -38,7 +38,7 @@ DefinitionBlock(
#include "acpi/thermal.asl"
#include <cpu/intel/fsp_model_406dx/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -27,7 +27,7 @@ DefinitionBlock(
#include <soc/intel/apollolake/acpi/globalnvs.asl>
/* CPU */
#include <soc/intel/apollolake/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -38,7 +38,7 @@ DefinitionBlock(
// global NVS and variables
#include <soc/intel/fsp_baytrail/acpi/globalnvs.asl>
#include <soc/intel/fsp_baytrail/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -38,7 +38,7 @@ DefinitionBlock(
#include "acpi/thermal.asl"
#include <cpu/intel/fsp_model_406dx/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -32,7 +32,7 @@ DefinitionBlock(
#include <soc/intel/skylake/acpi/globalnvs.asl>
// CPU
#include <soc/intel/skylake/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -32,7 +32,7 @@ DefinitionBlock(
/* global NVS and variables */
#include <acpi/globalnvs.asl>
#include <acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -36,7 +36,7 @@ DefinitionBlock(
//#include "acpi/gpe.asl"
// CPU
#include <soc/intel/broadwell/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -39,7 +39,7 @@ DefinitionBlock(
// General Purpose Events
//#include "acpi/gpe.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -28,7 +28,7 @@ DefinitionBlock(
{
// Some generic macros
#include "acpi/platform.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>

View File

@ -28,7 +28,7 @@ DefinitionBlock(
{
#include "acpi/platform.asl"
#include "acpi/gpe.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>

View File

@ -39,7 +39,7 @@ DefinitionBlock(
// global NVS and variables
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -39,7 +39,7 @@ DefinitionBlock(
// global NVS and variables
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -27,7 +27,7 @@ DefinitionBlock(
{
// Some generic macros
#include "acpi/platform.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>

View File

@ -39,7 +39,7 @@ DefinitionBlock(
// global NVS and variables
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -39,7 +39,7 @@ DefinitionBlock(
// global NVS and variables
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -39,7 +39,7 @@ DefinitionBlock(
// global NVS and variables
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -28,7 +28,7 @@ DefinitionBlock(
{
// Some generic macros
#include "acpi/platform.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
// global NVS and variables

View File

@ -39,7 +39,7 @@ DefinitionBlock(
// global NVS and variables
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -40,7 +40,7 @@ DefinitionBlock(
/* General Purpose Events */
#include "acpi/gpe.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -39,7 +39,7 @@ DefinitionBlock(
// global NVS and variables
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -39,7 +39,7 @@ DefinitionBlock(
// global NVS and variables
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -38,7 +38,7 @@ DefinitionBlock(
// global NVS and variables
#include <soc/intel/fsp_baytrail/acpi/globalnvs.asl>
#include <soc/intel/fsp_baytrail/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -33,7 +33,7 @@ DefinitionBlock(
/* General Purpose Events */
#include "acpi/gpe.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -30,7 +30,7 @@ DefinitionBlock(
#include <soc/intel/broadwell/acpi/globalnvs.asl>
/* CPU */
#include <soc/intel/broadwell/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -32,7 +32,7 @@ DefinitionBlock(
#include <soc/intel/skylake/acpi/globalnvs.asl>
// CPU
#include <soc/intel/skylake/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -37,7 +37,7 @@ DefinitionBlock(
#include "acpi/alsd.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -38,7 +38,7 @@ DefinitionBlock(
// General Purpose Events
//#include "acpi/gpe.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -38,7 +38,7 @@ DefinitionBlock(
#include "acpi/thermal.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -29,7 +29,7 @@ DefinitionBlock(
{
// Some generic macros
#include "acpi/platform.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>

View File

@ -39,7 +39,7 @@ DefinitionBlock(
// global NVS and variables
#include <soc/intel/denverton_ns/acpi/globalnvs.asl>
#include <soc/intel/denverton_ns/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -30,7 +30,7 @@ DefinitionBlock(
#include <soc/intel/apollolake/acpi/globalnvs.asl>
/* CPU */
#include <soc/intel/apollolake/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -38,7 +38,7 @@ DefinitionBlock(
// global NVS and variables
#include <soc/intel/fsp_baytrail/acpi/globalnvs.asl>
#include <soc/intel/fsp_baytrail/acpi/cpu.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)

View File

@ -1,35 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* These come from the dynamically created CPU SSDT */
External (\_PR.CNOT, MethodObj)
/* Notify OS to re-read CPU tables */
Method (PNOT)
{
\_PR.CNOT (0x81)
}
/* Notify OS to re-read CPU _PPC limit */
Method (PPCN)
{
\_PR.CNOT (0x80)
}
/* Notify OS to re-read Throttle Limit tables */
Method (TNOT)
{
\_PR.CNOT (0x82)
}

View File

@ -1,36 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* These come from the dynamically created CPU SSDT */
External (\_PR.CNOT, MethodObj)
/* Notify OS to re-read CPU tables */
Method (PNOT)
{
\_PR.CNOT (0x81)
}
/* Notify OS to re-read CPU _PPC limit */
Method (PPCN)
{
\_PR.CNOT (0x80)
}
/* Notify OS to re-read Throttle Limit tables */
Method (TNOT)
{
\_PR.CNOT (0x82)
}

View File

@ -1,36 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* These come from the dynamically created CPU SSDT */
External (\_PR.CNOT, MethodObj)
/* Notify OS to re-read CPU tables */
Method (PNOT)
{
\_PR.CNOT (0x81)
}
/* Notify OS to re-read CPU _PPC limit */
Method (PPCN)
{
\_PR.CNOT (0x80)
}
/* Notify OS to re-read Throttle Limit tables */
Method (TNOT)
{
\_PR.CNOT (0x82)
}

View File

@ -1,35 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* These come from the dynamically created CPU SSDT */
External (\_PR.CNOT, MethodObj)
/* Notify OS to re-read CPU tables */
Method (PNOT)
{
\_PR.CNOT (0x81)
}
/* Notify OS to re-read CPU _PPC limit */
Method (PPCN)
{
\_PR.CNOT (0x80)
}
/* Notify OS to re-read Throttle Limit tables */
Method (TNOT)
{
\_PR.CNOT (0x82)
}

View File

@ -1,35 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* These come from the dynamically created CPU SSDT */
External (\_PR.CNOT, MethodObj)
/* Notify OS to re-read CPU tables */
Method (PNOT)
{
\_PR.CNOT (0x81)
}
/* Notify OS to re-read CPU _PPC limit */
Method (PPCN)
{
\_PR.CNOT (0x80)
}
/* Notify OS to re-read Throttle Limit tables */
Method (TNOT)
{
\_PR.CNOT (0x82)
}

View File

@ -1,37 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
* Copyright (C) 2014 - 2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
/* These come from the dynamically created CPU SSDT */
External (\_PR.CNOT, MethodObj)
/* Notify OS to re-read CPU tables */
Method (PNOT)
{
\_PR.CNOT (0x81)
}
/* Notify OS to re-read CPU _PPC limit */
Method (PPCN)
{
\_PR.CNOT (0x80)
}
/* Notify OS to re-read Throttle Limit tables */
Method (TNOT)
{
\_PR.CNOT (0x82)
}

View File

@ -1,36 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* These come from the dynamically created CPU SSDT */
External (\_PR.CNOT, MethodObj)
/* Notify OS to re-read CPU tables */
Method (PNOT)
{
\_PR.CNOT (0x81)
}
/* Notify OS to re-read CPU _PPC limit */
Method (PPCN)
{
\_PR.CNOT (0x80)
}
/* Notify OS to re-read Throttle Limit tables */
Method (TNOT)
{
\_PR.CNOT (0x82)
}

View File

@ -1,35 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* These come from the dynamically created CPU SSDT */
External (\_PR.CNOT, MethodObj)
/* Notify OS to re-read CPU tables */
Method (PNOT)
{
\_PR.CNOT (0x81)
}
/* Notify OS to re-read CPU _PPC limit */
Method (PPCN)
{
\_PR.CNOT (0x80)
}
/* Notify OS to re-read Throttle Limit tables */
Method (TNOT)
{
\_PR.CNOT (0x82)
}

View File

@ -1,35 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* These come from the dynamically created CPU SSDT */
External (\_PR.CNOT, MethodObj)
/* Notify OS to re-read CPU tables */
Method (PNOT)
{
\_PR.CNOT (0x81)
}
/* Notify OS to re-read CPU _PPC limit */
Method (PPCN)
{
\_PR.CNOT (0x80)
}
/* Notify OS to re-read Throttle Limit tables */
Method (TNOT)
{
\_PR.CNOT (0x82)
}