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soc/intel/fsp_broadwell_de: examine ACM status at romstage entry 

When INTEL_TXT is set, at romstage entry check if startup ACM worked correctly
by probing TXT_ERROR register.

Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I6f423df8b05dc44220a9bad3674f687bac94e335
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42713
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jonathan Zhang 2020-06-19 12:41:13 -07:00 committed by Philipp Deppenwiese
parent ea7fde7070
commit aae448601c
1 changed files with 9 additions and 0 deletions
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9
src/soc/intel/fsp_broadwell_de/romstage/romstage.c
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@ -38,6 +38,9 @@
#include <soc/ubox.h> #include <soc/ubox.h>
#include <build.h> #include <build.h>
#include <security/intel/txt/txt.h>
#include <security/intel/txt/txt_register.h>
static void init_rtc(void) static void init_rtc(void)
{ {
u16 gen_pmcon3 = pci_read_config16(PCI_DEV(0, LPC_DEV, LPC_FUNC), GEN_PMCON_3); u16 gen_pmcon3 = pci_read_config16(PCI_DEV(0, LPC_DEV, LPC_FUNC), GEN_PMCON_3);
@ -156,6 +159,12 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header)
early_iio_hide(); early_iio_hide();
timestamp_add_now(TS_BEFORE_INITRAM); timestamp_add_now(TS_BEFORE_INITRAM);
post_code(0x48); post_code(0x48);
if (CONFIG(INTEL_TXT)) {
printk(BIOS_DEBUG, "Check TXT_ERROR register\n");
intel_txt_log_acm_error(read32((void *)TXT_ERROR));
}
/* /*
* Call early init to initialize memory and chipset. This function returns * Call early init to initialize memory and chipset. This function returns
* to the romstage_main_continue function with a pointer to the HOB * to the romstage_main_continue function with a pointer to the HOB