mainboard/lenovo: Add new port L520
Add support for Lenovo Thinkpad L520. The files are generated by autoport, and are successfully tested on the board. L520 has got 4MiB flash chip, that contains a "slim" ME with 1.2MiB only. The flash IC has to be desoldered, as it won't be accessible in circuit. It is located on top of the mainboard right under the touchpad. Test-setup: Extract the following blobs from vendor BIOS: * Intel Flash Descriptor * Intel Management Engine * Intel VBios The laptop has been externaly flashed. It was able to turn on the display and load SeaBIOS. Latest debian has been booted from harddisk. Latest fedora has been booted from USB flash drive. The following hardware has been tested and is working: * Display using Option Rom * PCIe wifi * Ethernet * Keyboard, trackpoint and touchpad * Some Fn functions keys * Volume Keys (except mic mute) * Status LEDs * Audio (headphone jack only) * USB ports * Native raminit dual channel (2 DDR3-1333 DIMMs tested) * SATA cdrom * SATA harddrive Broken: * Some Fn functions keys * Microphone mute button * Speakers (but headphone jack gives sound) Untested: * Expansion slot * SD card slot * Docking station * Native gfx init The EHCI debug port is the first one on the right side. Change-Id: Ic8943799b953bde09ff1daf8427ce5125a0778ca Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18003 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Patrick Rudolph
Martin Roth
parent
847bbb8b1b
commit
aae6e9cfe9
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@ -0,0 +1,70 @@
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if BOARD_LENOVO_L520
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select BOARD_ROMSIZE_KB_4096
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select CPU_INTEL_SOCKET_RPGA989
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select EC_LENOVO_H8
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select EC_LENOVO_PMH7
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select INTEL_INT15
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select SANDYBRIDGE_IVYBRIDGE_LVDS
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select SERIRQ_CONTINUOUS_MODE
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select SOUTHBRIDGE_INTEL_BD82X6X
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select SYSTEM_TYPE_LAPTOP
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select USE_NATIVE_RAMINIT
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select DRIVERS_LENOVO_HYBRID_GRAPHICS
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config HAVE_IFD_BIN
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bool
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default n
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config HAVE_ME_BIN
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bool
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default n
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config MAINBOARD_DIR
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string
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default lenovo/l520
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config MAINBOARD_PART_NUMBER
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string
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default "ThinkPad L520"
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config VGA_BIOS_FILE
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string
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default "pci8086,0126.rom"
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config VGA_BIOS_ID
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string
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default "8086,0126"
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config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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hex
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default 0x21dd
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config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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hex
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default 0x17aa
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config MMCONF_BASE_ADDRESS
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hex
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default 0xf0000000
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config DRAM_RESET_GATE_GPIO
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int
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default 10
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config MAX_CPUS
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int
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default 8
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config USBDEBUG_HCD_INDEX
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int
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default 2
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endif
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@ -0,0 +1,2 @@
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config BOARD_LENOVO_L520
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bool "ThinkPad L520"
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@ -0,0 +1,19 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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romstage-y += romstage.c
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romstage-y += gpio.c
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ramstage-y += acpi_tables.c
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smm-y += smihandler.c
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (c) 2016 Patrick Rudolph <siro@das-labor.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <ec/lenovo/h8/acpi/ec.asl>
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Scope(\_SB.PCI0.LPCB.EC)
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{
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}
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@ -0,0 +1,28 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (c) 2016 Patrick Rudolph <siro@das-labor.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Method(_WAK,1)
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{
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/* ME may not be up yet. */
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Store (0, \_TZ.MEB1)
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Store (0, \_TZ.MEB2)
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Return(Package(){0,0})
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}
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Method(_PTS,1)
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{
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\_SB.PCI0.LPCB.EC.RADI(0)
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}
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@ -0,0 +1,17 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (c) 2016 Patrick Rudolph <siro@das-labor.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <drivers/pc80/pc/ps2_controller.asl>
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@ -0,0 +1,43 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2016 Patrick Rudolph <siro@das-labor.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/bd82x6x/nvs.h>
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#include "thermal.h"
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static void acpi_update_thermal_table(global_nvs_t *gnvs)
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{
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gnvs->tcrt = CRITICAL_TEMPERATURE;
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gnvs->tpsv = PASSIVE_TEMPERATURE;
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}
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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/* Disable USB ports in S3 by default */
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gnvs->s3u0 = 0;
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gnvs->s3u1 = 0;
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/* Disable USB ports in S5 by default */
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gnvs->s5u0 = 0;
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gnvs->s5u1 = 0;
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// the lid is open by default.
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gnvs->lids = 1;
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acpi_update_thermal_table(gnvs);
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}
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Category: laptop
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ROM package: SOIC-8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: n
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Release year: 2011
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boot_option=Fallback
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baud_rate=115200
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debug_level=Spew
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power_on_after_fail=Disable
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nmi=Enable
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volume=0x3
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first_battery=Primary
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bluetooth=Enable
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wwan=Enable
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wlan=Enable
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touchpad=Enable
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sata_mode=AHCI
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fn_ctrl_swap=Disable
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sticky_fn=Disable
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trackpoint=Enable
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hyper_threading=Enable
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backlight=Both
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hybrid_graphics_mode=Integrated Only
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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## Copyright (C) 2014 Vladimir Serbinenko
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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# Status Register A
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# -----------------------------------------------------------------
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# Status Register B
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# -----------------------------------------------------------------
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# Status Register C
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#96 4 r 0 status_c_rsvd
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#100 1 r 0 uf_flag
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#101 1 r 0 af_flag
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#102 1 r 0 pf_flag
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#103 1 r 0 irqf_flag
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# -----------------------------------------------------------------
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# Status Register D
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#104 7 r 0 status_d_rsvd
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#111 1 r 0 valid_cmos_ram
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# -----------------------------------------------------------------
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# Diagnostic Status Register
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#112 8 r 0 diag_rsvd1
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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#120 264 r 0 unused
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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#390 2 r 0 unused?
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# -----------------------------------------------------------------
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# coreboot config options: console
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392 3 e 5 baud_rate
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395 4 e 6 debug_level
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#399 1 r 0 unused
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#400 8 r 0 reserved for century byte
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# coreboot config options: southbridge
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408 1 e 1 nmi
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409 2 e 7 power_on_after_fail
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# coreboot config options: EC
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411 1 e 8 first_battery
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412 1 e 1 bluetooth
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413 1 e 1 wwan
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414 1 e 1 touchpad
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415 1 e 1 wlan
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416 1 e 1 trackpoint
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417 1 e 1 fn_ctrl_swap
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418 1 e 1 sticky_fn
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#419 2 r 0 unused
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421 1 e 9 sata_mode
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422 2 e 10 backlight
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# coreboot config options: cpu
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424 1 e 2 hyper_threading
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#425 7 r 0 unused
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# coreboot config options: northbridge
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432 3 e 11 gfx_uma_size
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435 2 e 12 hybrid_graphics_mode
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#437 3 r 0 unused
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440 8 h 0 volume
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# SandyBridge MRC Scrambler Seed values
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896 32 r 0 mrc_scrambler_seed
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928 32 r 0 mrc_scrambler_seed_s3
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960 16 r 0 mrc_scrambler_seed_chk
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# coreboot config options: check sums
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984 16 h 0 check_sum
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 1 Emergency
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6 2 Alert
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6 3 Critical
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6 4 Error
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6 5 Warning
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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8 0 Secondary
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8 1 Primary
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9 0 AHCI
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9 1 Compatible
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10 0 Both
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10 1 Keyboard only
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10 2 Thinklight only
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10 3 None
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11 0 32M
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11 1 64M
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11 2 96M
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11 3 128M
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11 4 160M
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11 5 192M
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11 6 224M
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12 0 Integrated Only
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12 1 Discrete Only
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# -----------------------------------------------------------------
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checksums
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checksum 392 415 984
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@ -0,0 +1,174 @@
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chip northbridge/intel/sandybridge
|
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register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
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register "gfx.link_frequency_270_mhz" = "0"
|
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register "gfx.ndid" = "3"
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register "gfx.use_spread_spectrum_clock" = "0"
|
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register "gpu_cpu_backlight" = "0x00000000"
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register "gpu_dp_b_hotplug" = "0"
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register "gpu_dp_c_hotplug" = "0"
|
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register "gpu_dp_d_hotplug" = "0"
|
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register "gpu_panel_port_select" = "0"
|
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register "gpu_panel_power_backlight_off_delay" = "0"
|
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register "gpu_panel_power_backlight_on_delay" = "0"
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register "gpu_panel_power_cycle_delay" = "0"
|
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register "gpu_panel_power_down_delay" = "0"
|
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register "gpu_panel_power_up_delay" = "0"
|
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register "gpu_pch_backlight" = "0x00000000"
|
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|
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# Override fuse bits that hard-code the value to 666 Mhz
|
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register "max_mem_clock_mhz" = "933"
|
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|
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device cpu_cluster 0x0 on
|
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chip cpu/intel/socket_rPGA989
|
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device lapic 0x0 on
|
||||
end
|
||||
end
|
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chip cpu/intel/model_206ax
|
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register "c1_acpower" = "1"
|
||||
register "c1_battery" = "1"
|
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register "c2_acpower" = "3"
|
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register "c2_battery" = "3"
|
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register "c3_acpower" = "5"
|
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register "c3_battery" = "5"
|
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device lapic 0xacac off
|
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end
|
||||
end
|
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end
|
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|
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device domain 0x0 on
|
||||
device pci 00.0 on # Host bridge Host bridge
|
||||
subsystemid 0x17aa 0x21dd
|
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end
|
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device pci 01.0 on # PCIe Bridge for discrete graphics
|
||||
end
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||||
device pci 02.0 on # Internal graphics VGA controller
|
||||
subsystemid 0x17aa 0x21dd
|
||||
end
|
||||
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
|
||||
register "c2_latency" = "0x0065"
|
||||
register "docking_supported" = "1"
|
||||
register "gen1_dec" = "0x007c1611"
|
||||
register "gen2_dec" = "0x00040069"
|
||||
register "gen3_dec" = "0x000c0701"
|
||||
register "gen4_dec" = "0x00000000"
|
||||
register "gpi13_routing" = "2"
|
||||
register "gpi6_routing" = "2"
|
||||
register "p_cnt_throttling_supported" = "1"
|
||||
register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 1, 0, 0, 0 }"
|
||||
register "pcie_port_coalesce" = "1"
|
||||
register "sata_interface_speed_support" = "0x3"
|
||||
register "sata_port_map" = "0x3b"
|
||||
device pci 16.0 on # Management Engine Interface 1
|
||||
subsystemid 0x17aa 0x21dd
|
||||
end
|
||||
device pci 16.1 off # Management Engine Interface 2
|
||||
end
|
||||
device pci 16.2 off # Management Engine IDE-R
|
||||
end
|
||||
device pci 16.3 off # Management Engine KT
|
||||
end
|
||||
device pci 19.0 off # Intel Gigabit Ethernet
|
||||
end
|
||||
device pci 1a.0 on # USB2 EHCI #2
|
||||
subsystemid 0x17aa 0x21dd
|
||||
end
|
||||
device pci 1b.0 on # High Definition Audio Audio controller
|
||||
subsystemid 0x17aa 0x21dd
|
||||
end
|
||||
device pci 1c.0 on # PCIe Port #1
|
||||
subsystemid 0x17aa 0x21dd
|
||||
end
|
||||
device pci 1c.1 on # PCIe Port #2
|
||||
subsystemid 0x17aa 0x21dd
|
||||
end
|
||||
device pci 1c.2 on # PCIe Port #3
|
||||
subsystemid 0x17aa 0x21dd
|
||||
end
|
||||
device pci 1c.3 on # PCIe Port #4
|
||||
subsystemid 0x17aa 0x21dd
|
||||
end
|
||||
device pci 1c.4 on # PCIe Port #5
|
||||
subsystemid 0x17aa 0x21dd
|
||||
end
|
||||
device pci 1c.5 on # PCIe Port #6
|
||||
subsystemid 0x17aa 0x21dd
|
||||
end
|
||||
device pci 1c.6 off # PCIe Port #7
|
||||
end
|
||||
device pci 1c.7 off # PCIe Port #8
|
||||
end
|
||||
device pci 1d.0 on # USB2 EHCI #1
|
||||
subsystemid 0x17aa 0x21dd
|
||||
end
|
||||
device pci 1e.0 off # PCI bridge
|
||||
end
|
||||
device pci 1f.0 on # LPC bridge PCI-LPC bridge
|
||||
subsystemid 0x17aa 0x21dd
|
||||
chip ec/lenovo/pmh7
|
||||
register "backlight_enable" = "0x01"
|
||||
register "dock_event_enable" = "0x01"
|
||||
device pnp ff.1 on # dummy
|
||||
end
|
||||
end
|
||||
chip ec/lenovo/h8
|
||||
register "config0" = "0xa7"
|
||||
register "config1" = "0x09"
|
||||
register "config2" = "0xa0"
|
||||
register "config3" = "0xc2"
|
||||
|
||||
register "beepmask0" = "0x00"
|
||||
register "beepmask1" = "0x86"
|
||||
register "has_power_management_beeps" = "0"
|
||||
register "event2_enable" = "0xff"
|
||||
register "event3_enable" = "0xff"
|
||||
register "event4_enable" = "0xff"
|
||||
register "event5_enable" = "0xff"
|
||||
register "event6_enable" = "0xff"
|
||||
register "event7_enable" = "0xff"
|
||||
register "event8_enable" = "0xff"
|
||||
register "event9_enable" = "0xff"
|
||||
register "eventa_enable" = "0xff"
|
||||
register "eventb_enable" = "0xff"
|
||||
register "eventc_enable" = "0xff"
|
||||
register "eventd_enable" = "0xff"
|
||||
register "evente_enable" = "0xff"
|
||||
|
||||
device pnp ff.2 on # dummy
|
||||
io 0x60 = 0x62
|
||||
io 0x62 = 0x66
|
||||
io 0x64 = 0x1600
|
||||
io 0x66 = 0x1604
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 1f.2 on # SATA Controller 1
|
||||
subsystemid 0x17aa 0x21dd
|
||||
end
|
||||
device pci 1f.3 on # SMBus
|
||||
subsystemid 0x17aa 0x21dd
|
||||
chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip
|
||||
device i2c 54 on
|
||||
end
|
||||
device i2c 55 on
|
||||
end
|
||||
device i2c 56 on
|
||||
end
|
||||
device i2c 57 on
|
||||
end
|
||||
device i2c 5c on
|
||||
end
|
||||
device i2c 5d on
|
||||
end
|
||||
device i2c 5e on
|
||||
end
|
||||
device i2c 5f on
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 1f.5 off # SATA Controller 2
|
||||
end
|
||||
device pci 1f.6 off # Thermal
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
|
||||
#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
|
||||
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
|
||||
#define EC_LENOVO_H8_ME_WORKAROUND 1
|
||||
#define THINKPAD_EC_GPE 22
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x03, // DSDT revision: ACPI v3.0
|
||||
"COREv4", // OEM id
|
||||
"COREBOOT", // OEM table id
|
||||
0x20141018 // OEM revision
|
||||
)
|
||||
{
|
||||
// Some generic macros
|
||||
#include "acpi/platform.asl"
|
||||
#include <cpu/intel/model_206ax/acpi/cpu.asl>
|
||||
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
|
||||
/* global NVS and variables. */
|
||||
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
|
||||
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
|
||||
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
|
||||
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
|
||||
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,220 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
* Copyright (C) 2016 Patrick Rudolph <siro@das-labor.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
.gpio0 = GPIO_MODE_GPIO,
|
||||
.gpio1 = GPIO_MODE_GPIO,
|
||||
.gpio2 = GPIO_MODE_GPIO,
|
||||
.gpio3 = GPIO_MODE_GPIO,
|
||||
.gpio4 = GPIO_MODE_GPIO,
|
||||
.gpio5 = GPIO_MODE_GPIO,
|
||||
.gpio6 = GPIO_MODE_GPIO,
|
||||
.gpio7 = GPIO_MODE_GPIO,
|
||||
.gpio8 = GPIO_MODE_GPIO,
|
||||
.gpio12 = GPIO_MODE_GPIO,
|
||||
.gpio13 = GPIO_MODE_GPIO,
|
||||
.gpio15 = GPIO_MODE_GPIO,
|
||||
.gpio16 = GPIO_MODE_GPIO,
|
||||
.gpio17 = GPIO_MODE_GPIO,
|
||||
.gpio19 = GPIO_MODE_GPIO,
|
||||
.gpio21 = GPIO_MODE_GPIO,
|
||||
.gpio22 = GPIO_MODE_GPIO,
|
||||
.gpio23 = GPIO_MODE_GPIO,
|
||||
.gpio24 = GPIO_MODE_GPIO,
|
||||
.gpio27 = GPIO_MODE_GPIO,
|
||||
.gpio28 = GPIO_MODE_GPIO,
|
||||
.gpio29 = GPIO_MODE_GPIO,
|
||||
.gpio30 = GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
.gpio0 = GPIO_DIR_OUTPUT,
|
||||
.gpio1 = GPIO_DIR_INPUT,
|
||||
.gpio2 = GPIO_DIR_OUTPUT,
|
||||
.gpio3 = GPIO_DIR_INPUT,
|
||||
.gpio4 = GPIO_DIR_OUTPUT,
|
||||
.gpio5 = GPIO_DIR_OUTPUT,
|
||||
.gpio6 = GPIO_DIR_INPUT,
|
||||
.gpio7 = GPIO_DIR_INPUT,
|
||||
.gpio8 = GPIO_DIR_OUTPUT,
|
||||
.gpio12 = GPIO_DIR_OUTPUT,
|
||||
.gpio13 = GPIO_DIR_OUTPUT,
|
||||
.gpio15 = GPIO_DIR_OUTPUT,
|
||||
.gpio16 = GPIO_DIR_INPUT,
|
||||
.gpio17 = GPIO_DIR_INPUT,
|
||||
.gpio19 = GPIO_DIR_OUTPUT,
|
||||
.gpio21 = GPIO_DIR_OUTPUT,
|
||||
.gpio22 = GPIO_DIR_INPUT,
|
||||
.gpio23 = GPIO_DIR_OUTPUT,
|
||||
.gpio24 = GPIO_DIR_OUTPUT,
|
||||
.gpio27 = GPIO_DIR_OUTPUT,
|
||||
.gpio28 = GPIO_DIR_OUTPUT,
|
||||
.gpio29 = GPIO_DIR_OUTPUT,
|
||||
.gpio30 = GPIO_DIR_OUTPUT,
|
||||
};
|
||||
|
||||
const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
.gpio0 = GPIO_LEVEL_HIGH,
|
||||
.gpio2 = GPIO_LEVEL_HIGH,
|
||||
.gpio4 = GPIO_LEVEL_HIGH,
|
||||
.gpio5 = GPIO_LEVEL_HIGH,
|
||||
.gpio8 = GPIO_LEVEL_LOW,
|
||||
.gpio12 = GPIO_LEVEL_LOW,
|
||||
.gpio13 = GPIO_LEVEL_LOW,
|
||||
.gpio15 = GPIO_LEVEL_LOW,
|
||||
.gpio19 = GPIO_LEVEL_LOW,
|
||||
.gpio21 = GPIO_LEVEL_LOW,
|
||||
.gpio23 = GPIO_LEVEL_LOW,
|
||||
.gpio24 = GPIO_LEVEL_HIGH,
|
||||
.gpio27 = GPIO_LEVEL_HIGH,
|
||||
.gpio28 = GPIO_LEVEL_HIGH,
|
||||
.gpio29 = GPIO_LEVEL_HIGH,
|
||||
.gpio30 = GPIO_LEVEL_HIGH,
|
||||
};
|
||||
|
||||
const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||
.gpio24 = GPIO_RESET_RSMRST,
|
||||
.gpio30 = GPIO_RESET_RSMRST,
|
||||
};
|
||||
|
||||
const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
.gpio1 = GPIO_INVERT,
|
||||
.gpio6 = GPIO_INVERT,
|
||||
};
|
||||
|
||||
const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
};
|
||||
|
||||
const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
.gpio33 = GPIO_MODE_GPIO,
|
||||
.gpio35 = GPIO_MODE_GPIO,
|
||||
.gpio36 = GPIO_MODE_GPIO,
|
||||
.gpio37 = GPIO_MODE_GPIO,
|
||||
.gpio38 = GPIO_MODE_GPIO,
|
||||
.gpio39 = GPIO_MODE_GPIO,
|
||||
.gpio40 = GPIO_MODE_GPIO,
|
||||
.gpio41 = GPIO_MODE_GPIO,
|
||||
.gpio48 = GPIO_MODE_GPIO,
|
||||
.gpio49 = GPIO_MODE_GPIO,
|
||||
.gpio50 = GPIO_MODE_GPIO,
|
||||
.gpio51 = GPIO_MODE_GPIO,
|
||||
.gpio52 = GPIO_MODE_GPIO,
|
||||
.gpio53 = GPIO_MODE_GPIO,
|
||||
.gpio54 = GPIO_MODE_GPIO,
|
||||
.gpio55 = GPIO_MODE_GPIO,
|
||||
.gpio57 = GPIO_MODE_GPIO,
|
||||
.gpio59 = GPIO_MODE_GPIO,
|
||||
.gpio60 = GPIO_MODE_GPIO,
|
||||
.gpio61 = GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
.gpio33 = GPIO_DIR_OUTPUT,
|
||||
.gpio35 = GPIO_DIR_OUTPUT,
|
||||
.gpio36 = GPIO_DIR_INPUT,
|
||||
.gpio37 = GPIO_DIR_INPUT,
|
||||
.gpio38 = GPIO_DIR_INPUT,
|
||||
.gpio39 = GPIO_DIR_INPUT,
|
||||
.gpio40 = GPIO_DIR_INPUT,
|
||||
.gpio41 = GPIO_DIR_INPUT,
|
||||
.gpio48 = GPIO_DIR_INPUT,
|
||||
.gpio49 = GPIO_DIR_INPUT,
|
||||
.gpio50 = GPIO_DIR_OUTPUT,
|
||||
.gpio51 = GPIO_DIR_OUTPUT,
|
||||
.gpio52 = GPIO_DIR_OUTPUT,
|
||||
.gpio53 = GPIO_DIR_OUTPUT,
|
||||
.gpio54 = GPIO_DIR_OUTPUT,
|
||||
.gpio55 = GPIO_DIR_OUTPUT,
|
||||
.gpio57 = GPIO_DIR_INPUT,
|
||||
.gpio60 = GPIO_DIR_OUTPUT,
|
||||
.gpio61 = GPIO_DIR_OUTPUT,
|
||||
};
|
||||
|
||||
const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
.gpio33 = GPIO_LEVEL_LOW,
|
||||
.gpio35 = GPIO_LEVEL_HIGH,
|
||||
.gpio50 = GPIO_LEVEL_HIGH,
|
||||
.gpio51 = GPIO_LEVEL_HIGH,
|
||||
.gpio52 = GPIO_LEVEL_HIGH,
|
||||
.gpio53 = GPIO_LEVEL_HIGH,
|
||||
.gpio54 = GPIO_LEVEL_LOW,
|
||||
.gpio55 = GPIO_LEVEL_HIGH,
|
||||
.gpio57 = GPIO_LEVEL_LOW,
|
||||
.gpio60 = GPIO_LEVEL_LOW,
|
||||
.gpio61 = GPIO_LEVEL_LOW,
|
||||
};
|
||||
|
||||
const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||
};
|
||||
|
||||
const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
.gpio64 = GPIO_MODE_GPIO,
|
||||
.gpio65 = GPIO_MODE_GPIO,
|
||||
.gpio66 = GPIO_MODE_GPIO,
|
||||
.gpio67 = GPIO_MODE_GPIO,
|
||||
.gpio68 = GPIO_MODE_GPIO,
|
||||
.gpio69 = GPIO_MODE_GPIO,
|
||||
.gpio70 = GPIO_MODE_GPIO,
|
||||
.gpio71 = GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
.gpio64 = GPIO_DIR_OUTPUT,
|
||||
.gpio65 = GPIO_DIR_OUTPUT,
|
||||
.gpio66 = GPIO_DIR_OUTPUT,
|
||||
.gpio67 = GPIO_DIR_INPUT,
|
||||
.gpio68 = GPIO_DIR_INPUT,
|
||||
.gpio69 = GPIO_DIR_OUTPUT,
|
||||
.gpio70 = GPIO_DIR_OUTPUT,
|
||||
.gpio71 = GPIO_DIR_OUTPUT,
|
||||
};
|
||||
|
||||
const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
.gpio64 = GPIO_LEVEL_LOW,
|
||||
.gpio65 = GPIO_LEVEL_LOW,
|
||||
.gpio66 = GPIO_LEVEL_LOW,
|
||||
.gpio69 = GPIO_LEVEL_LOW,
|
||||
.gpio70 = GPIO_LEVEL_HIGH,
|
||||
.gpio71 = GPIO_LEVEL_LOW,
|
||||
};
|
||||
|
||||
const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
||||
};
|
||||
|
||||
const struct pch_gpio_map mainboard_gpio_map = {
|
||||
.set1 = {
|
||||
.mode = &pch_gpio_set1_mode,
|
||||
.direction = &pch_gpio_set1_direction,
|
||||
.level = &pch_gpio_set1_level,
|
||||
.blink = &pch_gpio_set1_blink,
|
||||
.invert = &pch_gpio_set1_invert,
|
||||
.reset = &pch_gpio_set1_reset,
|
||||
},
|
||||
.set2 = {
|
||||
.mode = &pch_gpio_set2_mode,
|
||||
.direction = &pch_gpio_set2_direction,
|
||||
.level = &pch_gpio_set2_level,
|
||||
.reset = &pch_gpio_set2_reset,
|
||||
},
|
||||
.set3 = {
|
||||
.mode = &pch_gpio_set3_mode,
|
||||
.direction = &pch_gpio_set3_direction,
|
||||
.level = &pch_gpio_set3_level,
|
||||
.reset = &pch_gpio_set3_reset,
|
||||
},
|
||||
};
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
* Copyright (C) 2016 Patrick Rudolph <siro@das-labor.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
0x10ec0269, /* Codec Vendor / Device ID: Realtek */
|
||||
0x17aa21de, /* Subsystem ID */
|
||||
|
||||
0x0000000b, /* Number of 4 dword sets */
|
||||
/* NID 0x01: Subsystem ID. */
|
||||
AZALIA_SUBVENDOR(0x0, 0x17aa21de),
|
||||
|
||||
/* NID 0x12. */
|
||||
AZALIA_PIN_CFG(0x0, 0x12, 0x99a30920),
|
||||
|
||||
/* NID 0x14. */
|
||||
AZALIA_PIN_CFG(0x0, 0x14, 0x99130110),
|
||||
|
||||
/* NID 0x17. */
|
||||
AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),
|
||||
|
||||
/* NID 0x18. */
|
||||
AZALIA_PIN_CFG(0x0, 0x18, 0x03a11830),
|
||||
|
||||
/* NID 0x19. */
|
||||
AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0),
|
||||
|
||||
/* NID 0x1a. */
|
||||
AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0),
|
||||
|
||||
/* NID 0x1b. */
|
||||
AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0),
|
||||
|
||||
/* NID 0x1d. */
|
||||
AZALIA_PIN_CFG(0x0, 0x1d, 0x40079a2d),
|
||||
|
||||
/* NID 0x1e. */
|
||||
AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0),
|
||||
|
||||
/* NID 0x21. */
|
||||
AZALIA_PIN_CFG(0x0, 0x21, 0x0321101f),
|
||||
0x80862805, /* Codec Vendor / Device ID: Intel */
|
||||
0x80860101, /* Subsystem ID */
|
||||
|
||||
0x00000004, /* Number of 4 dword sets */
|
||||
/* NID 0x01: Subsystem ID. */
|
||||
AZALIA_SUBVENDOR(0x3, 0x80860101),
|
||||
|
||||
/* NID 0x05. */
|
||||
AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),
|
||||
|
||||
/* NID 0x06. */
|
||||
AZALIA_PIN_CFG(0x3, 0x06, 0x18560020),
|
||||
|
||||
/* NID 0x07. */
|
||||
AZALIA_PIN_CFG(0x3, 0x07, 0x18560030),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[0] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
* Copyright (C) 2016 Patrick Rudolph <siro@das-labor.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/device.h>
|
||||
#include <drivers/intel/gma/int15.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
#include <ec/lenovo/h8/h8.h>
|
||||
|
||||
static void mainboard_init(device_t dev)
|
||||
{
|
||||
RCBA32(0x38c8) = 0x00000000;
|
||||
RCBA32(0x38c4) = 0x00000000;
|
||||
RCBA32(0x38c0) = 0x00000000;
|
||||
}
|
||||
|
||||
static void mainboard_enable(device_t dev)
|
||||
{
|
||||
dev->ops->init = mainboard_init;
|
||||
|
||||
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
|
||||
}
|
||||
|
||||
void h8_mainboard_init_dock(void)
|
||||
{
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
* Copyright (C) 2016 Patrick Rudolph <siro@das-labor.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <northbridge/intel/sandybridge/sandybridge.h>
|
||||
#include <northbridge/intel/sandybridge/raminit_native.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
|
||||
void pch_enable_lpc(void)
|
||||
{
|
||||
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c0f);
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c1611);
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00040069);
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0701);
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000);
|
||||
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000);
|
||||
}
|
||||
|
||||
void rcba_config(void)
|
||||
{
|
||||
/* Disable devices. */
|
||||
RCBA32(0x3414) = 0x00000000;
|
||||
RCBA32(0x3418) = 0x00000000;
|
||||
|
||||
}
|
||||
const struct southbridge_usb_port mainboard_usb_ports[] = {
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
};
|
||||
|
||||
void mainboard_early_init(int s3resume)
|
||||
{
|
||||
}
|
||||
|
||||
void mainboard_config_superio(void)
|
||||
{
|
||||
}
|
||||
|
||||
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
|
||||
{
|
||||
read_spd(&spd[0], 0x50, id_only);
|
||||
read_spd(&spd[2], 0x52, id_only);
|
||||
}
|
||||
|
|
@ -0,0 +1,102 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
* Copyright (C) 2016 Patrick Rudolph <siro@das-labor.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <ec/acpi/ec.h>
|
||||
#include <ec/lenovo/h8/h8.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
|
||||
#define GPE_EC_SCI 6
|
||||
/* FIXME: check this */
|
||||
#define GPE_EC_WAKE 13
|
||||
|
||||
static void mainboard_smm_init(void)
|
||||
{
|
||||
printk(BIOS_DEBUG, "initializing SMI\n");
|
||||
/* Enable 0x1600/0x1600 register pair */
|
||||
ec_set_bit(0x00, 0x05);
|
||||
}
|
||||
|
||||
int mainboard_io_trap_handler(int smif)
|
||||
{
|
||||
static int smm_initialized;
|
||||
|
||||
if (!smm_initialized) {
|
||||
mainboard_smm_init();
|
||||
smm_initialized = 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mainboard_smi_handle_ec_sci(void)
|
||||
{
|
||||
u8 status = inb(EC_SC);
|
||||
u8 event;
|
||||
|
||||
if (!(status & EC_SCI_EVT))
|
||||
return;
|
||||
|
||||
event = ec_query();
|
||||
printk(BIOS_DEBUG, "EC event %02x\n", event);
|
||||
}
|
||||
|
||||
void mainboard_smi_gpi(u32 gpi_sts)
|
||||
{
|
||||
if (gpi_sts & (1 << GPE_EC_SCI))
|
||||
mainboard_smi_handle_ec_sci();
|
||||
}
|
||||
|
||||
int mainboard_smi_apmc(u8 data)
|
||||
{
|
||||
switch (data) {
|
||||
case APM_CNT_ACPI_ENABLE:
|
||||
/* use 0x1600/0x1604 to prevent races with userspace */
|
||||
ec_set_ports(0x1604, 0x1600);
|
||||
/* route EC_SCI to SCI */
|
||||
gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI);
|
||||
/* discard all events, and enable attention */
|
||||
ec_write(0x80, 0x01);
|
||||
break;
|
||||
case APM_CNT_ACPI_DISABLE:
|
||||
/* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
|
||||
provide a EC query function */
|
||||
ec_set_ports(0x66, 0x62);
|
||||
/* route EC_SCI to SMI */
|
||||
gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI);
|
||||
/* discard all events, and enable attention */
|
||||
ec_write(0x80, 0x01);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void mainboard_smi_sleep(u8 slp_typ)
|
||||
{
|
||||
if (slp_typ == 3) {
|
||||
u8 ec_wake = ec_read(0x32);
|
||||
/* If EC wake events are enabled, enable wake on EC WAKE GPE. */
|
||||
if (ec_wake & 0x14) {
|
||||
/* Redirect EC WAKE GPE to SCI. */
|
||||
gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
* Copyright (C) 2016 Patrick Rudolph <siro@das-labor.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef L520_THERMAL_H
|
||||
#define L520_THERMAL_H
|
||||
|
||||
/* Temperature which OS will shutdown at */
|
||||
#define CRITICAL_TEMPERATURE 100
|
||||
|
||||
/* Temperature which OS will throttle CPU */
|
||||
#define PASSIVE_TEMPERATURE 90
|
||||
|
||||
#endif /* L520_THERMAL_H */
|
||||
Loading…
Reference in New Issue