GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/dedede: source soc_common_config from variants overridetree 

All variants are overriding soc_common_config, so source it from
overridetree and remove entry from baseboard devicetree.
Only keeping chipset lockdown config in baseboard which will be
common across all the variants.

BUG=None
BRANCH=None
TEST=Checked code compilation and lockdown config is applied to all variants

Change-Id: I23714b721a6bb0bac785f046586790a98dc5b646
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
This commit is contained in:
Maulik V Vaghela 2020-06-06 16:36:05 +05:30 committed by Subrata Banik
parent 4dbe84e432
commit aaebfa800c
1 changed files with 5 additions and 37 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

42
src/mainboard/google/dedede/variants/baseboard/devicetree.cb
View File

@ -141,43 +141,11 @@ chip soc/intel/jasperlake
# Enable Speed Shift Technology support # Enable Speed Shift Technology support
register "speed_shift_enable" = "1" register "speed_shift_enable" = "1"
# Intel Common SoC Config # chipset_lockdown configuration
#+-------------------+---------------------------+ # Use below format to override value in overridetree.cb if required
#| Field | Value | # format:
#+-------------------+---------------------------+ # register "common_soc_config.<variable_name>" = "value"
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| I2C0 | Trackpad |
#| I2C1 | Digitizer |
#| I2C2 | Touchscreen |
#| I2C3 | Camera |
#| I2C4 | Audio |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
},
}"
device domain 0 on device domain 0 on
device pci 00.0 on end # Host Bridge device pci 00.0 on end # Host Bridge