rockchip/rk3399: fix DRAM gate training issue
The differential signal of DQS needs to keep low level before gate training. RPULL will connect 4Kn from PADP to VSS and a 4Kn from PADN to VDDQ to ensure it. But if it has PHY side ODT connected at this time, it will change the DQS signal level. So it needs to disable PHY side ODT when doing gate training. BRANCH=None BUG=None TEST=boot from bob Change-Id: I56ace8375067aa0bb54d558bc28172b431b92ca5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: cb024042c7297a6b17c41cf650990cd342b1376f Original-Change-Id: I33cf743c3793a2765a21e5121ce7351410b9e19d Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/448278 Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com> Original-Tested-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Reviewed-on: https://review.coreboot.org/18582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
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@ -465,9 +465,9 @@ struct rk3399_sdram_params params = {
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0x00000000, /* DENALI_PI_65_DATA */
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0x04060002, /* DENALI_PI_66_DATA */
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0x04010401, /* DENALI_PI_67_DATA */
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0x01080801, /* DENALI_PI_68_DATA */
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0x04020201, /* DENALI_PI_69_DATA */
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0x01080804, /* DENALI_PI_70_DATA */
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0x00080801, /* DENALI_PI_68_DATA */
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0x00020001, /* DENALI_PI_69_DATA */
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0x00080004, /* DENALI_PI_70_DATA */
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0x00000000, /* DENALI_PI_71_DATA */
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0x04040000, /* DENALI_PI_72_DATA */
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0x0c0c0c04, /* DENALI_PI_73_DATA */
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@ -466,9 +466,9 @@ struct rk3399_sdram_params params = {
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0x00000000, /* DENALI_PI_65_DATA */
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0x03060002, /* DENALI_PI_66_DATA */
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0x03010301, /* DENALI_PI_67_DATA */
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0x01080801, /* DENALI_PI_68_DATA */
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0x04020201, /* DENALI_PI_69_DATA */
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0x01080804, /* DENALI_PI_70_DATA */
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0x00080801, /* DENALI_PI_68_DATA */
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0x00020001, /* DENALI_PI_69_DATA */
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0x00080004, /* DENALI_PI_70_DATA */
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0x00000000, /* DENALI_PI_71_DATA */
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0x03030000, /* DENALI_PI_72_DATA */
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0x0a0a0a03, /* DENALI_PI_73_DATA */
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@ -682,7 +682,7 @@ struct rk3399_sdram_params params = {
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0x00b30080, /* DENALI_PHY_77_DATA */
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0x00000003, /* DENALI_PHY_78_DATA */
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0x00000000, /* DENALI_PHY_79_DATA */
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0x00030000, /* DENALI_PHY_80_DATA */
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0x00020000, /* DENALI_PHY_80_DATA */
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0x00000200, /* DENALI_PHY_81_DATA */
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0x00000000, /* DENALI_PHY_82_DATA */
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0x51315152, /* DENALI_PHY_83_DATA */
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@ -810,7 +810,7 @@ struct rk3399_sdram_params params = {
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0x00b30080, /* DENALI_PHY_205_DATA */
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0x00000003, /* DENALI_PHY_206_DATA */
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0x00000000, /* DENALI_PHY_207_DATA */
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0x00030000, /* DENALI_PHY_208_DATA */
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0x00020000, /* DENALI_PHY_208_DATA */
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0x00000200, /* DENALI_PHY_209_DATA */
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0x00000000, /* DENALI_PHY_210_DATA */
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0x51315152, /* DENALI_PHY_211_DATA */
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@ -938,7 +938,7 @@ struct rk3399_sdram_params params = {
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0x00b30080, /* DENALI_PHY_333_DATA */
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0x00000003, /* DENALI_PHY_334_DATA */
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0x00000000, /* DENALI_PHY_335_DATA */
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0x00030000, /* DENALI_PHY_336_DATA */
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0x00020000, /* DENALI_PHY_336_DATA */
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0x00000200, /* DENALI_PHY_337_DATA */
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0x00000000, /* DENALI_PHY_338_DATA */
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0x51315152, /* DENALI_PHY_339_DATA */
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@ -1066,7 +1066,7 @@ struct rk3399_sdram_params params = {
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0x00b30080, /* DENALI_PHY_461_DATA */
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0x00000003, /* DENALI_PHY_462_DATA */
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0x00000000, /* DENALI_PHY_463_DATA */
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0x00030000, /* DENALI_PHY_464_DATA */
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0x00020000, /* DENALI_PHY_464_DATA */
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0x00000200, /* DENALI_PHY_465_DATA */
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0x00000000, /* DENALI_PHY_466_DATA */
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0x51315152, /* DENALI_PHY_467_DATA */
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@ -466,9 +466,9 @@ struct rk3399_sdram_params params = {
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0x00000000, /* DENALI_PI_65_DATA */
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0x04060002, /* DENALI_PI_66_DATA */
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0x04010401, /* DENALI_PI_67_DATA */
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0x01080801, /* DENALI_PI_68_DATA */
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0x04020201, /* DENALI_PI_69_DATA */
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0x01080804, /* DENALI_PI_70_DATA */
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0x00080801, /* DENALI_PI_68_DATA */
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0x00020001, /* DENALI_PI_69_DATA */
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0x00080004, /* DENALI_PI_70_DATA */
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0x00000000, /* DENALI_PI_71_DATA */
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0x04040000, /* DENALI_PI_72_DATA */
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0x0c0c0c04, /* DENALI_PI_73_DATA */
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@ -466,9 +466,9 @@ struct rk3399_sdram_params params = {
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0x00000000, /* DENALI_PI_65_DATA */
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0x03060002, /* DENALI_PI_66_DATA */
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0x03010301, /* DENALI_PI_67_DATA */
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0x01080801, /* DENALI_PI_68_DATA */
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0x04020201, /* DENALI_PI_69_DATA */
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0x01080804, /* DENALI_PI_70_DATA */
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0x00080801, /* DENALI_PI_68_DATA */
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0x00020001, /* DENALI_PI_69_DATA */
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0x00080004, /* DENALI_PI_70_DATA */
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0x00000000, /* DENALI_PI_71_DATA */
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0x03030000, /* DENALI_PI_72_DATA */
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0x0a0a0a03, /* DENALI_PI_73_DATA */
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@ -682,7 +682,7 @@ struct rk3399_sdram_params params = {
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0x00b30080, /* DENALI_PHY_77_DATA */
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0x00000003, /* DENALI_PHY_78_DATA */
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0x00000000, /* DENALI_PHY_79_DATA */
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0x00030000, /* DENALI_PHY_80_DATA */
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0x00020000, /* DENALI_PHY_80_DATA */
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0x00000200, /* DENALI_PHY_81_DATA */
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0x00000000, /* DENALI_PHY_82_DATA */
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0x51315152, /* DENALI_PHY_83_DATA */
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@ -810,7 +810,7 @@ struct rk3399_sdram_params params = {
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0x00b30080, /* DENALI_PHY_205_DATA */
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0x00000003, /* DENALI_PHY_206_DATA */
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0x00000000, /* DENALI_PHY_207_DATA */
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0x00030000, /* DENALI_PHY_208_DATA */
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0x00020000, /* DENALI_PHY_208_DATA */
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0x00000200, /* DENALI_PHY_209_DATA */
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0x00000000, /* DENALI_PHY_210_DATA */
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0x51315152, /* DENALI_PHY_211_DATA */
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@ -938,7 +938,7 @@ struct rk3399_sdram_params params = {
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0x00b30080, /* DENALI_PHY_333_DATA */
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0x00000003, /* DENALI_PHY_334_DATA */
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0x00000000, /* DENALI_PHY_335_DATA */
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0x00030000, /* DENALI_PHY_336_DATA */
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0x00020000, /* DENALI_PHY_336_DATA */
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0x00000200, /* DENALI_PHY_337_DATA */
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0x00000000, /* DENALI_PHY_338_DATA */
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0x51315152, /* DENALI_PHY_339_DATA */
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@ -1066,7 +1066,7 @@ struct rk3399_sdram_params params = {
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0x00b30080, /* DENALI_PHY_461_DATA */
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0x00000003, /* DENALI_PHY_462_DATA */
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0x00000000, /* DENALI_PHY_463_DATA */
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0x00030000, /* DENALI_PHY_464_DATA */
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0x00020000, /* DENALI_PHY_464_DATA */
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0x00000200, /* DENALI_PHY_465_DATA */
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0x00000000, /* DENALI_PHY_466_DATA */
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0x51315152, /* DENALI_PHY_467_DATA */
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@ -466,9 +466,9 @@ struct rk3399_sdram_params params = {
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0x00000000, /* DENALI_PI_65_DATA */
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0x04060002, /* DENALI_PI_66_DATA */
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0x04010401, /* DENALI_PI_67_DATA */
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0x01080801, /* DENALI_PI_68_DATA */
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0x04020201, /* DENALI_PI_69_DATA */
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0x01080804, /* DENALI_PI_70_DATA */
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0x00080801, /* DENALI_PI_68_DATA */
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0x00020001, /* DENALI_PI_69_DATA */
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0x00080004, /* DENALI_PI_70_DATA */
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0x00000000, /* DENALI_PI_71_DATA */
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0x04040000, /* DENALI_PI_72_DATA */
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0x0c0c0c04, /* DENALI_PI_73_DATA */
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@ -465,9 +465,9 @@ struct rk3399_sdram_params params = {
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0x00000000, /* DENALI_PI_65_DATA */
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0x03060002, /* DENALI_PI_66_DATA */
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0x03010301, /* DENALI_PI_67_DATA */
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0x01080801, /* DENALI_PI_68_DATA */
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0x04020201, /* DENALI_PI_69_DATA */
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0x01080804, /* DENALI_PI_70_DATA */
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0x00080801, /* DENALI_PI_68_DATA */
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0x00020001, /* DENALI_PI_69_DATA */
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0x00080004, /* DENALI_PI_70_DATA */
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0x00000000, /* DENALI_PI_71_DATA */
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0x03030000, /* DENALI_PI_72_DATA */
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0x0a0a0a03, /* DENALI_PI_73_DATA */
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@ -466,9 +466,9 @@ struct rk3399_sdram_params params = {
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0x00000000, /* DENALI_PI_65_DATA */
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0x04060002, /* DENALI_PI_66_DATA */
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0x04010401, /* DENALI_PI_67_DATA */
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0x01080801, /* DENALI_PI_68_DATA */
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0x04020201, /* DENALI_PI_69_DATA */
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0x01080804, /* DENALI_PI_70_DATA */
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0x00080801, /* DENALI_PI_68_DATA */
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0x00020001, /* DENALI_PI_69_DATA */
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0x00080004, /* DENALI_PI_70_DATA */
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0x00000000, /* DENALI_PI_71_DATA */
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0x04040000, /* DENALI_PI_72_DATA */
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0x0c0c0c04, /* DENALI_PI_73_DATA */
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@ -466,9 +466,9 @@ struct rk3399_sdram_params params = {
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0x00000000, /* DENALI_PI_65_DATA */
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0x03060002, /* DENALI_PI_66_DATA */
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0x03010301, /* DENALI_PI_67_DATA */
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0x01080801, /* DENALI_PI_68_DATA */
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0x04020201, /* DENALI_PI_69_DATA */
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0x01080804, /* DENALI_PI_70_DATA */
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0x00080801, /* DENALI_PI_68_DATA */
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0x00020001, /* DENALI_PI_69_DATA */
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0x00080004, /* DENALI_PI_70_DATA */
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0x00000000, /* DENALI_PI_71_DATA */
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0x03030000, /* DENALI_PI_72_DATA */
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0x0a0a0a03, /* DENALI_PI_73_DATA */
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@ -466,9 +466,9 @@ struct rk3399_sdram_params params = {
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0x00000000, /* DENALI_PI_65_DATA */
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0x04060002, /* DENALI_PI_66_DATA */
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0x04010401, /* DENALI_PI_67_DATA */
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0x01080801, /* DENALI_PI_68_DATA */
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0x04020201, /* DENALI_PI_69_DATA */
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0x01080804, /* DENALI_PI_70_DATA */
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0x00080801, /* DENALI_PI_68_DATA */
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0x00020001, /* DENALI_PI_69_DATA */
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0x00080004, /* DENALI_PI_70_DATA */
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0x00000000, /* DENALI_PI_71_DATA */
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0x04040000, /* DENALI_PI_72_DATA */
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0x0c0c0c04, /* DENALI_PI_73_DATA */
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@ -633,6 +633,7 @@ static int data_training(u32 channel,
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u32 i, tmp;
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u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
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u32 rank = sdram_params->ch[channel].rank;
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u32 reg_value = 0;
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/* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
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setbits_le32(&denali_phy[927], (1 << 22));
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@ -741,6 +742,28 @@ static int data_training(u32 channel,
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/* read gate training(LPDDR4,LPDDR3,DDR3 support) */
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if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) {
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/*
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* The differential signal of DQS needs to keep low level
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* before gate training. RPULL will connect 4Kn from PADP
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* to VSS and a 4Kn from PADN to VDDQ to ensure it.
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* But if it has PHY side ODT connect at this time,
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* it will change the DQS signal level. So disable PHY
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* side ODT before gate training and restore ODT state
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* after gate training.
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*/
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if (sdram_params->dramtype != LPDDR4) {
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reg_value = (read32(&denali_phy[6]) >> 24) & 0x7;
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/*
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* phy_dqs_tsel_enable_X 3bits
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* DENALI_PHY_6/134/262/390 offset_24
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*/
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clrbits_le32(&denali_phy[6], 0x7 << 24);
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clrbits_le32(&denali_phy[134], 0x7 << 24);
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clrbits_le32(&denali_phy[262], 0x7 << 24);
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clrbits_le32(&denali_phy[390], 0x7 << 24);
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}
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for (i = 0; i < rank; i++) {
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select_per_cs_training_index(channel, i);
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/* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */
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@ -784,6 +807,18 @@ static int data_training(u32 channel,
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write32((&denali_pi[175]), 0x00003f7c);
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}
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clrbits_le32(&denali_pi[80], 0x3 << 24);
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if (sdram_params->dramtype != LPDDR4) {
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/*
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* phy_dqs_tsel_enable_X 3bits
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* DENALI_PHY_6/134/262/390 offset_24
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*/
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tmp = reg_value << 24;
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clrsetbits_le32(&denali_phy[6], 0x7 << 24, tmp);
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clrsetbits_le32(&denali_phy[134], 0x7 << 24, tmp);
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clrsetbits_le32(&denali_phy[262], 0x7 << 24, tmp);
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clrsetbits_le32(&denali_phy[390], 0x7 << 24, tmp);
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}
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}
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/* read leveling(LPDDR4,LPDDR3,DDR3 support) */
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