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mb/google/kahlee: Do not enable SCI for H1_PCH_INT_ODL 

H1 is not a wake source and hence there is no need to configure SCI
GEVENT for it. This change drops PAD_SCI() configuration for GPIO_9
i.e. H1_PCH_INT_ODL.

BUG=b:159944426

Change-Id: Iec2285b76f9c5fa1b4b1be15128fea316fa04555
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh 2020-06-27 15:24:09 -07:00
parent 05d30605ec
commit aaff4017d0
1 changed files with 2 additions and 3 deletions
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5
src/mainboard/google/kahlee/variants/baseboard/gpio.c
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@ -18,9 +18,8 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
/* GPIO_6 - APU_RST_L / EC_SMI_ODL, SMI */ /* GPIO_6 - APU_RST_L / EC_SMI_ODL, SMI */
PAD_SMI(GPIO_6, PULL_UP, LEVEL_LOW), PAD_SMI(GPIO_6, PULL_UP, LEVEL_LOW),
/* GPIO_9 - H1_PCH_INT_ODL, SCI */ /* GPIO_9 - H1_PCH_INT_ODL */
PAD_INT(GPIO_9, PULL_UP, EDGE_LOW, STATUS), PAD_INT(GPIO_9, PULL_UP, EDGE_LOW, STATUS),
PAD_SCI(GPIO_9, PULL_UP, EDGE_LOW),
/* GPIO_15 - EC_IN_RW_OD */ /* GPIO_15 - EC_IN_RW_OD */
PAD_GPI(GPIO_15, PULL_UP), PAD_GPI(GPIO_15, PULL_UP),
@ -28,7 +27,7 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
/* GPIO_22 - EC_SCI_ODL, SCI */ /* GPIO_22 - EC_SCI_ODL, SCI */
PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW), PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW),
/* GPIO_24 - EC_PCH_WAKE_L */ /* GPIO_24 - EC_PCH_WAKE_L, SCI */
PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW), PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW),
/* GPIO_26 - APU_PCIE_RST_L */ /* GPIO_26 - APU_PCIE_RST_L */