Round 2 of i82801AX fixes to get it into a usable shape.
- Remove left-overs from more generic code in i82801xx times, and fix register names as needed. - Simplify IDE init code (and save some ROM space too). - Simplify PIRQ code. - Use u8 et al instead of uint8_t everywhere. - Random other fixes. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
3b8db81380
commit
ab06fb0cae
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@ -25,22 +25,16 @@
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#ifndef SOUTHBRIDGE_INTEL_I82801AX_CHIP_H
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#define SOUTHBRIDGE_INTEL_I82801AX_CHIP_H
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struct southbridge_intel_i82801ax_config {
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/**
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* Interrupt Routing configuration
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* If bit7 is 1, the interrupt is disabled.
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*/
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uint8_t pirqa_routing;
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uint8_t pirqb_routing;
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uint8_t pirqc_routing;
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uint8_t pirqd_routing;
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uint8_t pirqe_routing;
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uint8_t pirqf_routing;
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uint8_t pirqg_routing;
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uint8_t pirqh_routing;
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#include <stdint.h>
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uint8_t ide0_enable;
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uint8_t ide1_enable;
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struct southbridge_intel_i82801ax_config {
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u8 pirqa_routing;
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u8 pirqb_routing;
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u8 pirqc_routing;
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u8 pirqd_routing;
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u8 ide0_enable;
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u8 ide1_enable;
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};
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extern struct chip_operations southbridge_intel_i82801ax_ops;
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@ -27,38 +27,21 @@
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void i82801ax_enable(device_t dev)
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{
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unsigned int index = 0;
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uint16_t cur_disable_mask, new_disable_mask;
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u16 reg16, index;
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device_t lpc_dev;
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/* All 82801xx devices should be on bus 0. */
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unsigned int devfn = PCI_DEVFN(0x1f, 0); // LPC
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device_t lpc_dev = dev_find_slot(0, devfn); // 0
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/* Search for the 82801AA/AB LPC device (D31:F0) on PCI bus 0. */
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lpc_dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
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if (!lpc_dev)
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return;
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/* We're going to assume, perhaps incorrectly, that if a function
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* exists it can be disabled. Workarounds for ICH variants that don't
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* follow this should be done by checking the device ID.
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*/
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if (PCI_SLOT(dev->path.pci.devfn) == 31) {
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index = PCI_FUNC(dev->path.pci.devfn);
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} else if (PCI_SLOT(dev->path.pci.devfn) == 29) {
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index = 8 + PCI_FUNC(dev->path.pci.devfn);
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}
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/* Function 0 is a bit of an exception. */
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if (index == 0) {
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index = 14;
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}
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cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS);
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new_disable_mask = cur_disable_mask & ~(1 << index); /* Enable it. */
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if (!dev->enabled) {
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new_disable_mask |= (1 << index); /* Disable it, if desired. */
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}
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if (new_disable_mask != cur_disable_mask) {
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pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask);
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}
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reg16 = pci_read_config16(lpc_dev, FUNC_DIS);
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reg16 &= ~(1 << index); /* Enable device. */
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if (!dev->enabled)
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reg16 |= (1 << index); /* Disable device, if desired. */
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pci_write_config16(lpc_dev, FUNC_DIS, reg16);
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}
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struct chip_operations southbridge_intel_i82801ax_ops = {
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@ -26,37 +26,36 @@
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extern void i82801ax_enable(device_t dev);
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#endif
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#define SMBUS_IO_BASE 0x0f00
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#define PMBASE_ADDR 0x0400
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#define HPET_ADDR 0xfed00000
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#define PCI_DMA_CFG 0x90
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#define SERIRQ_CNTL 0x64
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#define GEN_CNTL 0xd0
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#define GEN_STS 0xd4
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#define GEN_STA 0xd4
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#define RTC_CONF 0xd8
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#define GEN_PMCON_3 0xa4
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#define PMBASE 0x40
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#define PMBASE_ADDR 0x0400 /* ACPI Base Address Register */
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#define ACPI_CNTL 0x44
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#define ACPI_EN (1 << 4)
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#define BIOS_CNTL 0x4E
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#define GPIO_BASE_ICH0_5 0x58 /* LPC GPIO Base Addr. Reg. (ICH0-ICH5) */
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#define GPIO_BASE_ICH6_9 0x48 /* LPC GPIO Base Address Register (ICH6-ICH9) */
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#define GPIO_CNTL_ICH0_5 0x5C /* LPC GPIO Control Register (ICH0-ICH5) */
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#define GPIO_CNTL_ICH6_9 0x4C /* LPC GPIO Control Register (ICH6-ICH9) */
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#define GPIO_BASE 0x58 /* GPIO Base Address Register */
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#define GPIO_CNTL 0x5C /* GPIO Control Register */
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#define GPIO_EN (1 << 4)
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#define PIRQA_ROUT 0x60
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#define PIRQB_ROUT 0x61
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#define PIRQC_ROUT 0x62
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#define PIRQD_ROUT 0x63
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#define PIRQE_ROUT 0x68
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#define PIRQF_ROUT 0x69
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#define PIRQG_ROUT 0x6A
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#define PIRQH_ROUT 0x6B
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#define FUNC_DIS 0xF2
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#define COM_DEC 0xE0 /* LPC I/F Communication Port Decode Ranges (ICH0-ICH5) */
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#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register (ICH6-ICH9) */
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#define LPC_EN_ICH0_5 0xE6 /* LPC IF Enables Register (ICH0-ICH5) */
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#define LPC_EN_ICH6_9 0x82 /* LPC IF Enables Register (ICH6-ICH9) */
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#define COM_DEC 0xE0 /* LPC I/F Comm. Port Decode Ranges */
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#define LPC_EN 0xE6 /* LPC IF Enables */
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// TODO: FDC_DEC etc.
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#define SBUS_NUM 0x19
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#define SUB_BUS_NUM 0x1A
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@ -77,14 +76,14 @@ extern void i82801ax_enable(device_t dev);
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#define RTC_POWER_FAILED (1 << 1)
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#define SLEEP_AFTER_POWER_FAIL (1 << 0)
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/* PCI Configuration Space (D31:F1) */
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/* IDE Timing registers (IDE_TIM) */
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#define IDE_TIM_PRI 0x40 /* IDE timings, primary */
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#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
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/* IDE_TIM bits */
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#define IDE_DECODE_ENABLE (1 << 15)
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/* PCI Configuration Space (D31:F3) */
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/* SMBus */
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#define SMB_BASE 0x20
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#define HOSTC 0x40
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@ -93,13 +92,7 @@ extern void i82801ax_enable(device_t dev);
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#define SMB_SMI_EN (1 << 1)
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#define HST_EN (1 << 0)
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/* SMBus I/O bits.
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* TODO: Does it matter where we put the SMBus IO base, as long as we keep
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* consistent and don't interfere with anything else?
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*/
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/* #define SMBUS_IO_BASE 0x1000 */
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#define SMBUS_IO_BASE 0x0f00
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/* SMBus I/O registers. */
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#define SMBHSTSTAT 0x0
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#define SMBHSTCTL 0x2
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#define SMBHSTCMD 0x3
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@ -107,14 +100,7 @@ extern void i82801ax_enable(device_t dev);
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#define SMBHSTDAT0 0x5
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#define SMBHSTDAT1 0x6
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#define SMBBLKDAT 0x7
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#define SMBTRNSADD 0x9
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#define SMBSLVDATA 0xa
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#define SMLINK_PIN_CTL 0xe
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#define SMBUS_PIN_CTL 0xf
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#define SMBUS_TIMEOUT (10 * 1000 * 100)
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/* HPET, if present */
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#define HPET_ADDR 0xfed00000
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#endif /* SOUTHBRIDGE_INTEL_I82801AX_I82801AX_H */
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#endif
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@ -19,8 +19,6 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* This code should work for all ICH* southbridges with AC97 audio/modem. */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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@ -61,4 +59,3 @@ static const struct pci_driver i82801ab_ac97_modem __pci_driver = {
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82801AB_AC97_MODEM,
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};
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@ -27,21 +27,10 @@
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static void enable_smbus(void)
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{
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device_t dev;
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uint16_t device_id;
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/* Set the SMBus device statically. */
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/* Set the SMBus device statically (D31:F3). */
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dev = PCI_DEV(0x0, 0x1f, 0x3);
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/* Check to make sure we've got the right device. */
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device_id = pci_read_config16(dev, 0x2);
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/* Clear bits 7-4 (the only bits that vary between models). */
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device_id &= 0xff0f;
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if (device_id != 0x2403) {
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die("Device not found, Corey probably screwed up!");
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}
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/* Set SMBus I/O base. */
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pci_write_config32(dev, SMB_BASE,
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SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
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@ -31,33 +31,24 @@ typedef struct southbridge_intel_i82801ax_config config_t;
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static void ide_init(struct device *dev)
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{
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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u16 reg16;
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config_t *conf = dev->chip_info;
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/* Enable IDE devices so the Linux IDE driver will work. */
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uint16_t ideTimingConfig;
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reg16 = pci_read_config16(dev, IDE_TIM_PRI);
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reg16 &= ~IDE_DECODE_ENABLE;
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if (!conf || conf->ide0_enable)
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reg16 |= IDE_DECODE_ENABLE;
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printk(BIOS_DEBUG, "IDE: %s: %s\n", "Primary IDE interface",
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conf->ide0_enable ? "on" : "off");
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pci_write_config16(dev, IDE_TIM_PRI, reg16);
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ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);
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ideTimingConfig &= ~IDE_DECODE_ENABLE;
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if (!config || config->ide0_enable) {
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/* Enable primary IDE interface. */
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ideTimingConfig |= IDE_DECODE_ENABLE;
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printk(BIOS_DEBUG, "IDE0: Primary IDE interface is enabled\n");
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} else {
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printk(BIOS_INFO, "IDE0: Primary IDE interface is disabled\n");
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}
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pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
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ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC);
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ideTimingConfig &= ~IDE_DECODE_ENABLE;
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if (!config || config->ide1_enable) {
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/* Enable secondary IDE interface. */
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ideTimingConfig |= IDE_DECODE_ENABLE;
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printk(BIOS_DEBUG, "IDE1: Secondary IDE interface is enabled\n");
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} else {
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printk(BIOS_INFO, "IDE1: Secondary IDE interface is disabled\n");
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}
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pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
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reg16 = pci_read_config16(dev, IDE_TIM_SEC);
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reg16 &= ~IDE_DECODE_ENABLE;
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if (!conf || conf->ide1_enable)
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reg16 |= IDE_DECODE_ENABLE;
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printk(BIOS_DEBUG, "IDE: %s: %s\n", "Primary IDE interface",
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conf->ide0_enable ? "on" : "off");
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pci_write_config16(dev, IDE_TIM_SEC, reg16);
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}
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static struct device_operations ide_ops = {
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@ -69,17 +60,16 @@ static struct device_operations ide_ops = {
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.enable = i82801ax_enable,
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};
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/* 82801AA */
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/* 82801AA (ICH) */
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static const struct pci_driver i82801aa_ide __pci_driver = {
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.ops = &ide_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = 0x2411,
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};
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/* 82801AB */
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/* 82801AB (ICH0) */
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static const struct pci_driver i82801ab_ide __pci_driver = {
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.ops = &ide_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = 0x2421,
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};
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@ -36,7 +36,7 @@
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typedef struct southbridge_intel_i82801ax_config config_t;
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/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
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/* PIRQ[n]_ROUT[3:0] - IRQ Routing (ISA compatible)
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* 0x00 - 0000 = Reserved
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* 0x01 - 0001 = Reserved
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* 0x02 - 0010 = Reserved
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@ -53,8 +53,10 @@ typedef struct southbridge_intel_i82801ax_config config_t;
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* 0x0D - 1101 = Reserved
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* 0x0E - 1110 = IRQ14
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* 0x0F - 1111 = IRQ15
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* PIRQ[n]_ROUT[7] - PIRQ Routing Control
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* 0x80 - The PIRQ is not routed.
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*
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* PIRQ[n]_ROUT[7] - Interrupt Routing Enable (IRQEN)
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* 0 - The PIRQ is routed to the ISA-compatible interrupt specified above.
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* 1 - The PIRQ is not routed to the 8259.
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*/
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#define PIRQA 0x03
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@ -66,25 +68,24 @@ typedef struct southbridge_intel_i82801ax_config config_t;
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* Use 0x0ef8 for a bitmap to cover all these IRQ's.
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* Use the defined IRQ values above or set mainboard
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* specific IRQ values in your mainboards Config.lb.
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*/
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*/
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static void i82801ax_enable_apic(struct device *dev)
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{
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uint32_t reg32;
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volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000;
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volatile uint32_t *ioapic_data = (volatile uint32_t *)0xfec00010;
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u32 reg32;
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volatile u32 *ioapic_index = (volatile u32 *)0xfec00000;
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volatile u32 *ioapic_data = (volatile u32 *)0xfec00010;
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/* Set ACPI base address (I/O space). */
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pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
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/* Enable ACPI I/O and power management. */
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pci_write_config8(dev, ACPI_CNTL, 0x10);
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/* Enable ACPI I/O range decode and ACPI power management. */
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pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
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reg32 = pci_read_config32(dev, GEN_CNTL);
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reg32 |= (3 << 7); /* Enable IOAPIC */
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reg32 |= (1 << 13); /* Coprocessor error enable */
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reg32 |= (1 << 1); /* Delayed transaction enable */
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reg32 |= (1 << 2); /* DMA collection buffer enable */
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reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */
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reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */
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reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */
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reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */
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pci_write_config32(dev, GEN_CNTL, reg32);
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printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
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@ -112,34 +113,22 @@ static void i82801ax_enable_serial_irqs(struct device *dev)
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/* TODO: Explain/#define the real meaning of these magic numbers. */
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}
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static void i82801ax_pirq_init(device_t dev, uint16_t ich_model)
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static void i82801ax_pirq_init(device_t dev)
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{
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/* Get the chip configuration */
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u8 reg8;
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config_t *config = dev->chip_info;
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if (config->pirqa_routing) {
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pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
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} else {
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pci_write_config8(dev, PIRQA_ROUT, PIRQA);
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}
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reg8 = (config->pirqa_routing) ? config->pirqa_routing : PIRQA;
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pci_write_config8(dev, PIRQA_ROUT, reg8);
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if (config->pirqb_routing) {
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pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
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} else {
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pci_write_config8(dev, PIRQB_ROUT, PIRQB);
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}
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reg8 = (config->pirqb_routing) ? config->pirqb_routing : PIRQB;
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pci_write_config8(dev, PIRQB_ROUT, reg8);
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if (config->pirqc_routing) {
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pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
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} else {
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pci_write_config8(dev, PIRQC_ROUT, PIRQC);
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}
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reg8 = (config->pirqc_routing) ? config->pirqc_routing : PIRQC;
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pci_write_config8(dev, PIRQC_ROUT, reg8);
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if (config->pirqd_routing) {
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pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
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} else {
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pci_write_config8(dev, PIRQD_ROUT, PIRQD);
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}
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reg8 = (config->pirqd_routing) ? config->pirqd_routing : PIRQD;
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pci_write_config8(dev, PIRQD_ROUT, reg8);
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}
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static void i82801ax_power_options(device_t dev)
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@ -172,10 +161,10 @@ static void i82801ax_power_options(device_t dev)
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}
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}
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static void gpio_init(device_t dev, uint16_t ich_model)
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static void gpio_init(device_t dev)
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{
|
||||
pci_write_config32(dev, GPIO_BASE_ICH0_5, (GPIO_BASE_ADDR | 1));
|
||||
pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
|
||||
pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1));
|
||||
pci_write_config8(dev, GPIO_CNTL, GPIO_EN);
|
||||
}
|
||||
|
||||
static void i82801ax_rtc_init(struct device *dev)
|
||||
|
|
@ -190,7 +179,7 @@ static void i82801ax_rtc_init(struct device *dev)
|
|||
reg8 &= ~(1 << 1); /* Preserve the power fail state. */
|
||||
pci_write_config8(dev, GEN_PMCON_3, reg8);
|
||||
}
|
||||
reg32 = pci_read_config32(dev, GEN_STS);
|
||||
reg32 = pci_read_config32(dev, GEN_STA);
|
||||
rtc_failed |= reg32 & (1 << 2);
|
||||
rtc_init(rtc_failed);
|
||||
|
||||
|
|
@ -213,7 +202,7 @@ static void i82801ax_lpc_route_dma(struct device *dev, uint8_t mask)
|
|||
pci_write_config16(dev, PCI_DMA_CFG, reg16);
|
||||
}
|
||||
|
||||
static void i82801ax_lpc_decode_en(device_t dev, uint16_t ich_model)
|
||||
static void i82801ax_lpc_decode_en(device_t dev)
|
||||
{
|
||||
/* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB.
|
||||
* LPT decode defaults to 0x378-0x37F and 0x778-0x77F.
|
||||
|
|
@ -221,13 +210,11 @@ static void i82801ax_lpc_decode_en(device_t dev, uint16_t ich_model)
|
|||
* We also need to set the value for LPC I/F Enables Register.
|
||||
*/
|
||||
pci_write_config8(dev, COM_DEC, 0x10);
|
||||
pci_write_config16(dev, LPC_EN_ICH0_5, 0x300F);
|
||||
pci_write_config16(dev, LPC_EN, 0x300F);
|
||||
}
|
||||
|
||||
static void lpc_init(struct device *dev)
|
||||
{
|
||||
uint16_t ich_model = pci_read_config16(dev, PCI_DEVICE_ID);
|
||||
|
||||
/* Set the value for PCI command register. */
|
||||
pci_write_config16(dev, PCI_COMMAND, 0x000f);
|
||||
|
||||
|
|
@ -237,13 +224,13 @@ static void lpc_init(struct device *dev)
|
|||
i82801ax_enable_serial_irqs(dev);
|
||||
|
||||
/* Setup the PIRQ. */
|
||||
i82801ax_pirq_init(dev, ich_model);
|
||||
i82801ax_pirq_init(dev);
|
||||
|
||||
/* Setup power options. */
|
||||
i82801ax_power_options(dev);
|
||||
|
||||
/* Set the state of the GPIO lines. */
|
||||
gpio_init(dev, ich_model);
|
||||
gpio_init(dev);
|
||||
|
||||
/* Initialize the real time clock. */
|
||||
i82801ax_rtc_init(dev);
|
||||
|
|
@ -255,7 +242,7 @@ static void lpc_init(struct device *dev)
|
|||
isa_dma_init();
|
||||
|
||||
/* Setup decode ports and LPC I/F enables. */
|
||||
i82801ax_lpc_decode_en(dev, ich_model);
|
||||
i82801ax_lpc_decode_en(dev);
|
||||
}
|
||||
|
||||
static void i82801ax_lpc_read_resources(device_t dev)
|
||||
|
|
@ -293,15 +280,16 @@ static struct device_operations lpc_ops = {
|
|||
.enable = i82801ax_enable,
|
||||
};
|
||||
|
||||
/* 82801AA (ICH) */
|
||||
static const struct pci_driver i82801aa_lpc __pci_driver = {
|
||||
.ops = &lpc_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x2410,
|
||||
};
|
||||
|
||||
/* 82801AB (ICH0) */
|
||||
static const struct pci_driver i82801ab_lpc __pci_driver = {
|
||||
.ops = &lpc_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x2420,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -26,16 +26,12 @@
|
|||
|
||||
static void pci_init(struct device *dev)
|
||||
{
|
||||
uint16_t reg16;
|
||||
u16 reg16;
|
||||
|
||||
/* Clear system errors */
|
||||
reg16 = pci_read_config16(dev, 0x06);
|
||||
reg16 |= 0xf900; /* Clear possible errors */
|
||||
pci_write_config16(dev, 0x06, reg16);
|
||||
|
||||
reg16 = pci_read_config16(dev, 0x1e);
|
||||
reg16 |= 0xf800; /* Clear possible errors */
|
||||
pci_write_config16(dev, 0x1e, reg16);
|
||||
/* Clear possible errors. */
|
||||
reg16 = pci_read_config16(dev, PCI_STATUS);
|
||||
reg16 |= 0xf900;
|
||||
pci_write_config16(dev, PCI_STATUS, reg16);
|
||||
}
|
||||
|
||||
static struct device_operations pci_ops = {
|
||||
|
|
@ -46,15 +42,16 @@ static struct device_operations pci_ops = {
|
|||
.scan_bus = pci_scan_bridge,
|
||||
};
|
||||
|
||||
/* 82801AA (ICH) */
|
||||
static const struct pci_driver i82801aa_pci __pci_driver = {
|
||||
.ops = &pci_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x2418,
|
||||
};
|
||||
|
||||
/* 82801AB (ICH0) */
|
||||
static const struct pci_driver i82801ab_pci __pci_driver = {
|
||||
.ops = &pci_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x2428,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -66,4 +66,3 @@ static const struct pci_driver i82801ab_smb __pci_driver = {
|
|||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_82801AB_SMB,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -18,8 +18,6 @@
|
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* This code should work for all ICH* southbridges with USB. */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
|
|
@ -53,4 +51,3 @@ static const struct pci_driver i82801ab_usb1 __pci_driver = {
|
|||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_82801AB_USB,
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue