From ab0a77453c86fe01ef142fcf1df5e1c11a16daf2 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Wed, 2 Jan 2019 14:04:02 +0100 Subject: [PATCH] cbmem_top: Fix comment and remove upper limit There's no such limit on 64 Bit coreboot builds. * Fix comment in cbmem.h * Remove 4 GiB limit on Cavium SoCs Tested on opencellular/elgon. Still boots Linux as payload. Change-Id: I8c9c6a5ff81bee48311e8bf8e383d1a032ea3a6d Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/30609 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Stefan Reinauer --- src/include/cbmem.h | 3 ++- src/soc/cavium/cn81xx/cbmem.c | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 59f4e105e1..680284acf1 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -70,7 +70,8 @@ void cbmem_top_init(void); /* Return the top address for dynamic cbmem. The address returned needs to * be consistent across romstage and ramstage, and it is required to be - * below 4GiB. + * below 4GiB for 32bit coreboot builds. On 64bit coreboot builds there's no + * upper limit. * x86 boards or chipsets must return NULL before the cbmem backing store has * been initialized. */ void *cbmem_top(void); diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c index 397fd263d7..bb6fa18f20 100644 --- a/src/soc/cavium/cn81xx/cbmem.c +++ b/src/soc/cavium/cn81xx/cbmem.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright 2014 Rockchip Inc. + * Copyright 2019 9Elements GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,6 +23,5 @@ void *cbmem_top(void) { /* Make sure not to overlap with reserved ATF scratchpad */ - return (void *)min((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB, - 4ULL * GiB); + return (void *)((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB); }