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mb/razer/blade_stealth_kbl: Disable UART #0 in devicetree 

FSP-S disables UART #0 as per the `SerialIoDevMode` settings.

Change-Id: Ic1f9f7ce6fd4f453200d563bd8556946eef1b287
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Mimoja <coreboot@mimoja.de>
This commit is contained in:
Angel Pons 2021-08-29 18:27:09 +02:00 committed by Felix Held
parent bbfb18c410
commit ab11f46219
1 changed files with 1 additions and 1 deletions
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src/mainboard/razer/blade_stealth_kbl/devicetree.cb
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@ -214,7 +214,7 @@ chip soc/intel/skylake
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1e.0 on end # Serial IO UART0
device pci 1e.0 off end # Serial IO UART0
device pci 1e.6 off end # SDXC
device pci 1f.0 on # LPC
chip drivers/pc80/tpm