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mb/amd/majolica: set PSPP policy to balanced 

BUG=b:188793754

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5fd0021170777c755ecb78d339aec05ff786710f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54932
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2021-05-25 20:53:19 +02:00
parent a7c410b286
commit ab1b606fd4
1 changed files with 2 additions and 0 deletions
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src/mainboard/amd/majolica/devicetree.cb
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@ -15,6 +15,8 @@ chip soc/amd/cezanne
register "s0ix_enable" = "true" register "s0ix_enable" = "true"
register "pspp_policy" = "DXIO_PSPP_BALANCED"
device domain 0 on device domain 0 on
device ref gpp_gfx_bridge_0 on end # MXM device ref gpp_gfx_bridge_0 on end # MXM
device ref gpp_bridge_0 on end # NVMe device ref gpp_bridge_0 on end # NVMe