mb/amd/majolica: set PSPP policy to balanced

BUG=b:188793754

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5fd0021170777c755ecb78d339aec05ff786710f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54932
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/amd/majolica/devicetree.cb

@@ -15,6 +15,8 @@ chip soc/amd/cezanne
 
 	register "s0ix_enable" = "true"
 
+	register "pspp_policy" = "DXIO_PSPP_BALANCED"
+
 	device domain 0 on
 		device ref gpp_gfx_bridge_0 on end # MXM
 		device ref gpp_bridge_0 on end # NVMe