diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 51322012d0..9d6f978a67 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -185,10 +185,6 @@ config EHCI_BAR
 	hex
 	default 0xd8000000
 
-config EHCI_DEBUG_OFFSET
-	hex
-	default 0xa0
-
 config SERIRQ_CONTINUOUS_MODE
 	bool
 	default y
diff --git a/src/soc/intel/broadwell/usb_debug.c b/src/soc/intel/broadwell/usb_debug.c
index fffebf00c6..683b4cc522 100644
--- a/src/soc/intel/broadwell/usb_debug.c
+++ b/src/soc/intel/broadwell/usb_debug.c
@@ -41,8 +41,6 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
 
 void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
 {
-	u32 tmp32;
-
 	if (!dev)
 		return;
 
@@ -51,9 +49,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
 
 	/* Enable access to the EHCI memory space registers. */
 	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
-
-	/* Force ownership of hte Debug Port to the EHCI controller. */
-	tmp32 = read32((void *)(base + CONFIG_EHCI_DEBUG_OFFSET));
-	tmp32 |= (1 << 30);
-	write32((void *)(base + CONFIG_EHCI_DEBUG_OFFSET), tmp32);
 }
diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig
index 4d2e89f316..ab85ec4c97 100644
--- a/src/southbridge/intel/fsp_rangeley/Kconfig
+++ b/src/southbridge/intel/fsp_rangeley/Kconfig
@@ -37,10 +37,6 @@ config EHCI_BAR
 	hex
 	default 0xfef00000
 
-config EHCI_DEBUG_OFFSET
-	hex
-	default 0xa0
-
 config SERIRQ_CONTINUOUS_MODE
 	bool
 	default n