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sb/intel/lynxpoint: Remove GPE0_{EN,STS}_2 defines 

By ACPI specification, those follow GPE0_EN bits in the register space.
Use sizeof() to replace the 2/4 offset previously used.

Change-Id: I27ada0b19b2cf5e8eca71f48bf103dcab1b3cc11
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2023-05-06 14:37:22 +03:00 committed by Lean Sheng Tan
parent 23d4614d8a
commit ab368d96d7
3 changed files with 6 additions and 8 deletions
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8
src/southbridge/intel/lynxpoint/elog.c
View File

@ -60,8 +60,8 @@ static void pch_log_gpe(void)
pch_log_standard_gpe(GPE0_EN, GPE0_STS);
/* GPIO 0-15 */
gpe0_en = inw(pmbase + GPE0_EN + 2);
gpe0_sts = inw(pmbase + GPE0_STS + 2) & gpe0_en;
gpe0_en = inw(pmbase + GPE0_EN + sizeof(uint16_t));
gpe0_sts = inw(pmbase + GPE0_STS + sizeof(uint16_t)) & gpe0_en;
for (i = 0; i <= 15; i++) {
if (gpe0_sts & (1 << i))
elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i);
@ -71,8 +71,8 @@ static void pch_log_gpe(void)
* Now check and log upper status bits
*/
gpe0_en = inl(pmbase + GPE0_EN_2);
gpe0_sts = inl(pmbase + GPE0_STS_2) & gpe0_en;
gpe0_en = inl(pmbase + GPE0_EN + sizeof(uint32_t));
gpe0_sts = inl(pmbase + GPE0_STS + sizeof(uint32_t)) & gpe0_en;
for (i = 0; i <= 31; i++) {
if (!gpe0_high_gpios[i])

2
src/southbridge/intel/lynxpoint/pch.h
View File

@ -666,12 +666,10 @@ void mainboard_config_rcba(void);
#define TCOSCI_STS (1 << 6)
#define SWGPE_STS (1 << 2)
#define HOT_PLUG_STS (1 << 1)
#define GPE0_STS_2 0x24
#define GPE0_EN 0x28
#define PME_B0_EN (1 << 13)
#define PME_EN (1 << 11)
#define TCOSCI_EN (1 << 6)
#define GPE0_EN_2 0x2c
#define SMI_EN 0x30
#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic
#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic

4
src/southbridge/intel/lynxpoint/pmutil.c
View File

@ -447,7 +447,7 @@ static u32 clear_lpt_gpe_status(void)
};
/* High bits */
print_gpe_status(reset_gpe_status(GPE0_STS_2, GPE0_EN_2),
print_gpe_status(reset_gpe_status(GPE0_STS + sizeof(uint32_t), GPE0_EN + sizeof(uint32_t)),
gpe0_sts_bits_high);
/* Standard GPE and GPIO 0-31 */
@ -507,7 +507,7 @@ void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4)
outl(set4, pmbase + LP_GPE0_EN_4);
} else {
outl(set1, pmbase + GPE0_EN);
outl(set2, pmbase + GPE0_EN_2);
outl(set2, pmbase + GPE0_EN + sizeof(u32));
}
}