soc/amd/picasso: Add UPD xhci0_force_gen1
Adding xhci0_force_gen1 UPD to force USB3 port to gen1. BUG=b:156314787 BRANCH=trembyle-bringup TEST=Build. Cq-Depend: chrome-internal:3013435 Change-Id: Iff3746e248625c253776c3bc3946d123b0635ffe Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2217662 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42216 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -103,6 +103,8 @@ struct soc_amd_picasso_config {
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SD_EMMC_EMMC_HS400,
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SD_EMMC_EMMC_HS300,
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} sd_emmc_config;
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uint8_t xhci0_force_gen1;
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};
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typedef struct soc_amd_picasso_config config_t;
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@ -95,6 +95,12 @@ static void fsp_fill_pcie_ddi_descriptors(FSP_S_CONFIG *scfg)
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fill_ddi_descriptors(scfg, fsp_ddi, num_ddi);
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}
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static void fsp_usb_oem_customization(FSP_S_CONFIG *scfg,
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const struct soc_amd_picasso_config *cfg)
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{
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scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1;
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}
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void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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{
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const struct soc_amd_picasso_config *cfg;
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@ -103,4 +109,5 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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cfg = config_of_soc();
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fsps_update_emmc_config(scfg, cfg);
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fsp_fill_pcie_ddi_descriptors(scfg);
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fsp_usb_oem_customization(scfg, cfg);
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}
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