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soc/amd/picasso: Add UPD xhci0_force_gen1 

Adding xhci0_force_gen1 UPD to force USB3 port to gen1.

BUG=b:156314787
BRANCH=trembyle-bringup
TEST=Build.

Cq-Depend: chrome-internal:3013435
Change-Id: Iff3746e248625c253776c3bc3946d123b0635ffe
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2217662
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42216
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Chris Wang 2020-05-28 21:16:34 +08:00 committed by Marshall Dawson
parent 34053fab21
commit ab3947a021
2 changed files with 9 additions and 0 deletions
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2
src/soc/amd/picasso/chip.h
View File

@ -103,6 +103,8 @@ struct soc_amd_picasso_config {
SD_EMMC_EMMC_HS400,
SD_EMMC_EMMC_HS300,
} sd_emmc_config;
uint8_t xhci0_force_gen1;
};
typedef struct soc_amd_picasso_config config_t;

7
src/soc/amd/picasso/fsp_params.c
View File

@ -95,6 +95,12 @@ static void fsp_fill_pcie_ddi_descriptors(FSP_S_CONFIG *scfg)
fill_ddi_descriptors(scfg, fsp_ddi, num_ddi);
}
static void fsp_usb_oem_customization(FSP_S_CONFIG *scfg,
const struct soc_amd_picasso_config *cfg)
{
scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1;
}
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{
const struct soc_amd_picasso_config *cfg;
@ -103,4 +109,5 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
cfg = config_of_soc();
fsps_update_emmc_config(scfg, cfg);
fsp_fill_pcie_ddi_descriptors(scfg);
fsp_usb_oem_customization(scfg, cfg);
}