Docs/acronyms.md: Fix build warnings & update some links
- Change all links to wikipedia to https. - Update some links to wikipedia that were incomplete. - Update a few links that are now broken. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If780e15997c499d1df975b436fd9af530f324eba Reviewed-on: https://review.coreboot.org/c/coreboot/+/77488 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Martin Roth
Felix Singer
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@ -24,7 +24,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
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* ACPI - The [**Advanced Configuration and Power
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Interface**](http://en.wikipedia.org/wiki/Advanced_Configuration_and_Power_Interface)
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is an industry standard for letting the OS control power management.
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* [http://www.acpi.info/](http://www.acpi.info/)
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* [https://uefi.org/specifications](https://uefi.org/specifications)
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* [http://kernelslacker.livejournal.com/88243.html](http://kernelslacker.livejournal.com/88243.html)
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* ADC - [**Analog-to-Digital Converter**](https://en.wikipedia.org/wiki/Analog-to-digital_converter)
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* ADL - Intel: [**Alder Lake**](https://en.wikichip.org/wiki/intel/microarchitectures/alder_lake)
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@ -32,11 +32,11 @@ Spec](https://uefi.org/specifications) for details, or run the tool
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* AESKL - Intel: AES Key Locker
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* AGESA - [**AMD Generic Encapsulated Software Architecture**](https://en.wikipedia.org/wiki/AGESA_)
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* AGP - The [**Accelerated Graphics
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Port**](http://en.wikipedia.org/wiki/Accelerated_Graphics_Port) is an
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Port**](https://en.wikipedia.org/wiki/Accelerated_Graphics_Port) is an
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older (1997-2004) point-to-point bus for video cards to communicate
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with the processor.
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* AHCI - The [**Advanced Host Controller
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Interface**](http://en.wikipedia.org/wiki/Advanced_Host_Controller_Interface)
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Interface**](https://en.wikipedia.org/wiki/Advanced_Host_Controller_Interface)
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is a standard register set for communicating with a SATA controller.
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* [http://www.intel.com/technology/serialata/ahci.htm](http://www.intel.com/technology/serialata/ahci.htm)
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* [http://download.intel.com/technology/serialata/pdf/rev1_3.pdf](http://download.intel.com/technology/serialata/pdf/rev1_3.pdf)
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@ -54,7 +54,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
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* AMPL - AMD: [**Advanced Platform Management Link**](https://web.archive.org/web/20220509053546/https://developer.amd.com/wordpress/media/2012/10/419181.pdf) - Also referred to as
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SBI: Sideband Interface
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* AMT - Intel: [**Active Management Technology**](https://en.wikipedia.org/wiki/Intel_Active_Management_Technology)
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* ANSI - [**American National Standards Institute**](American_National_Standards_Institute)
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* ANSI - [**American National Standards Institute**](https://en.wikipedia.org/wiki/American_National_Standards_Institute)
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* AOAC - AMD: Always On, Always Connected
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* AP - Application processor - The main processor on the board (as
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opposed to the embedded controller or other processors that may be on
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@ -63,7 +63,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
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* APCB - AMD: AMD PSP Customization Block
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* API - [**Application Programming Interface**](https://en.wikipedia.org/wiki/API)
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* APIC - [**Advanced Programmable Interrupt
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Controller**](http://en.wikipedia.org/wiki/Advanced_Programmable_Interrupt_Controller)
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Controller**](https://en.wikipedia.org/wiki/Advanced_Programmable_Interrupt_Controller)
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this is an advanced version of a PIC that can handle interrupts from
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and for multiple CPUs. Modern systems usually have several APICs:
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Local APICs (LAPIC) are CPU-bound, IO-APICs are bridge-bound.
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@ -98,7 +98,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
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## B
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* BAR - [**Base Address Register**](http://en.wikipedia.org/wiki/Base_Address_Register) This generally refers to one of the
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* BAR - [**Base Address Register**](https://en.wikipedia.org/wiki/Base_Address_Register) This generally refers to one of the
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base address registers in the PCI config space of a PCI device
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* Baud - [**Baud**](https://en.wikipedia.org/wiki/Baud) - Not an acronym - Symbol rate unit of symbols per second, named
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after Émile Baudot
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@ -117,7 +117,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
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the entire 4GiB of the 32-bit address space. Also known as flat mode
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or [**Unreal mode**](https://en.wikipedia.org/wiki/Unreal_mode).
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* BIOS - [**Basic Input/Output
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System**](http://en.wikipedia.org/wiki/BIOS)
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System**](https://en.wikipedia.org/wiki/BIOS)
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* BIST - The [**Built-in Self Test**](https://en.wikipedia.org/wiki/Built-in_self-test) is a test run by the processor on
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itself when it is first started. Usually, any nonzero value indicates
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that the selftest failed.
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@ -183,7 +183,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
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generally used to describe a section of NVRAM (Non-volatile RAM), in
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this case a section battery-backed memory in the RTC (Real Time Clock)
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that is typically used to store BIOS settings.
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*[http://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory](http://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory)
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*[https://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory](https://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory)
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* CNL - Intel: [**Cannon Lake**](https://en.wikichip.org/wiki/intel/microarchitectures/cannon_lake) (formerly Skymont)
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* CNVi - Intel: [**Connectivity Integration**](https://en.wikipedia.org/wiki/CNVi)
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* CPL - x86: Current Privilege Level - Privilege levels range from 0-3; lower numbers are more privileged.
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@ -191,14 +191,14 @@ Spec](https://uefi.org/specifications) for details, or run the tool
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* CPPC - AMD: Collaborative Processor Performance Controls
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* CPS - Characters Per Second
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* CPU - [**Central Processing
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Unit**](http://en.wikipedia.org/wiki/Central_processing_unit)
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Unit**](https://en.wikipedia.org/wiki/Central_processing_unit)
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* CPUID - x86: [**CPU Identification**](https://en.wikipedia.org/wiki/CPUID) opcode
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* Cr50 - Google: The first generation Google Security Chip (GSC) used on
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ChromeOS devices.
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* CRB - Customer Reference Board
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* CRLF - Carriage Return, Line Feed - \\r\\n - The standard window EOL
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(End-of-Line) marker.
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* crt0 - [**C Run Time 0**](http://en.wikipedia.org/wiki/Crt0)
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* crt0 - [**C Run Time 0**](https://en.wikipedia.org/wiki/Crt0)
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* crt0s - crt0 Source code
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* CRT - [**Cathode Ray Tube**](https://en.wikipedia.org/wiki/Cathode-ray_tube)
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* CSE - Intel: Converged Security Engine
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@ -226,7 +226,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
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still has power.
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* D3 Cold - ACPI Device power state: Power is completely removed from
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the device.
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* DASH - [**Desktop and mobile Architecture for System Hardware**](Desktop_and_mobile_Architecture_for_System_Hardware)
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* DASH - [**Desktop and mobile Architecture for System Hardware**](https://en.wikipedia.org/wiki/Desktop_and_mobile_Architecture_for_System_Hardware)
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* DB - DaughterBoard
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* DbC - USB: Debug Capability on the USB host controller
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* DC - Electricity: Direct Current
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@ -244,7 +244,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
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* DIMM - [**Dual Inline Memory Module**](https://en.wikipedia.org/wiki/DIMM)
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* DIP - [**Dual inline package**](https://en.wikipedia.org/wiki/Dual_in-line_package)
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* DMA - [**Direct Memory
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Access**](http://en.wikipedia.org/wiki/Direct_memory_access) Allows
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Access**](https://en.wikipedia.org/wiki/Direct_memory_access) Allows
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certain hardware subsystems within a computer to access system memory
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for reading and/or writing independently of the main CPU. Examples of
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systems that use DMA: Hard Disk Controller, Disk Drive Controller,
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@ -252,7 +252,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
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computers, as it allows devices of different speeds to communicate
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without subjecting the CPU to a massive interrupt load.
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* DMI - Direct Media Interface is a link/bus between CPU and PCH.
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* DMI - [**Desktop Management Interface**](Desktop_Management_Interface)
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* DMI - [**Desktop Management Interface**](https://en.wikipedia.org/wiki/Desktop_Management_Interface)
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* DMIC - Digital Microphone
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* DMTF - [**Distributed Management Task Force**](https://en.wikipedia.org/wiki/Distributed_Management_Task_Force)
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* DMZ - Demilitarized Zone
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@ -358,7 +358,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
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* FPDT - ACPI: Firmware Performance Data Table
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* FPGA - [**Field-Programmable Gate Array**](https://en.wikipedia.org/wiki/Field-programmable_gate_array)
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* Framebuffer - The
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[**framebuffer**](http://en.wikipedia.org/wiki/Framebuffer) is a part
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[**framebuffer**](https://en.wikipedia.org/wiki/Framebuffer) is a part
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of RAM in a computer which is allocated to hold the graphics
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information for one frame or picture. This information typically
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consists of color values for every pixel on the screen. A framebuffer
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@ -446,7 +446,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
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resume quickly from S3 if the system stays powered, and resume from
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the disk if power is lost.
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* Hypertransport - AMD: The
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[**Hypertransport**](http://en.wikipedia.org/wiki/Hypertransport) bus
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[**Hypertransport**](https://en.wikipedia.org/wiki/Hypertransport) bus
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is an older (2001-2017) high-speed electrical interconnection protocol
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specification between CPU, Memory, and (occasionally) peripheral
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devices. This was originally called the Lightning Data Transport
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@ -622,7 +622,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
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* MKBP - Matrix Keyboard Protocol
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* MMC - [**MultiMedia
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Card**](https://en.wikipedia.org/wiki/MultiMediaCard)
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* MMIO - [**Memory Mapped I/O**](http://en.wikipedia.org/wiki/MMIO)
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* MMIO - [**Memory Mapped I/O**](https://en.wikipedia.org/wiki/MMIO)
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allows peripherals' memory or registers to be accessed directly
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through the memory bus. When the memory bus size was very small, this
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was initially done by hiding any memory at that address, effectively
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@ -652,7 +652,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
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* MTS or MT/s - MegaTransfers per second
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* MTL - Intel: Meteor Lake
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* MTL - ARM: MHU Transport Layer
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* MTRR - [**Memory Type and Range Register**](http://en.wikipedia.org/wiki/MTRR)
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* MTRR - [**Memory Type and Range Register**](https://en.wikipedia.org/wiki/MTRR)
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allows to set the cache behaviour on memory access in x86. Basically,
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it tells the CPU how to cache certain ranges of memory
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(e.g. write-through, write-combining, write-back...). Memory ranges
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@ -731,17 +731,17 @@ Spec](https://uefi.org/specifications) for details, or run the tool
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* PCD - UEFI: Platform Configuration Database
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* PCH - Intel: [**Platform Controller Hub**](https://en.wikipedia.org/wiki/Platform_Controller_Hub)
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* PCI - [**Peripheral Control
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Interconnect**](http://en.wikipedia.org/wiki/Peripheral_Component_Interconnect)
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Interconnect**](https://en.wikipedia.org/wiki/Peripheral_Component_Interconnect)
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- Replaced generally by PCIe (PCI Express)
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* PCI Configuration Space - The [**PCI Config
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space**](http://en.wikipedia.org/wiki/PCI_Configuration_Space) is an
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space**](https://en.wikipedia.org/wiki/PCI_Configuration_Space) is an
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[address space](https://en.wikipedia.org/wiki/Address_space) for all
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PCI devices. Originally, this address space was accessed through an
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index/data pair by writing the address that you wanted to read/write
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into the I/O address 0xCF8, then reading or writing I/O Address 0xCFC.
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This has been updated to an MMIO method which increases each PCI
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function's configuration space from 256 bytes to 4K.
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* PCIe - [**PCI Express**](http://en.wikipedia.org/wiki/Pci_express)
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* PCIe - [**PCI Express**](https://en.wikipedia.org/wiki/Pci_express)
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* PCMCIA: Personal Computer Memory Card International Association
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* PCO - AMD: [**Picasso**](https://en.wikichip.org/wiki/amd/cores/picasso)
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* PCR: TPM: Platform Configuration Register
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@ -757,7 +757,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
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* PEP - Intel: Power Engine Plug-in
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* PEXVDD - Nvidia Power: PCIExpress Voltage
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* PHX - AMD: Phoenix SoC
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* PHY - [**PHYsical layer**](http://en.wikipedia.org/wiki/PHY) - The
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* PHY - [**PHYsical layer**](https://en.wikipedia.org/wiki/PHY) - The
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hardware that implements the send/receive functionality of a
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communication protocol.
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* PI - Platform Initialization
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@ -776,7 +776,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
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* PIT - Generally refers to the 8253/8254 [**Programmable Interval
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Timer**](https://en.wikipedia.org/wiki/Programmable_interval_timer).
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* PLCC - [**Plastic leaded chip
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carrier**](http://en.wikipedia.org/wiki/Plastic_leaded_chip_carrier)
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carrier**](https://en.wikipedia.org/wiki/Plastic_leaded_chip_carrier)
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* PLL - [**Phase-Locked
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Loop**](https://en.wikipedia.org/wiki/Phase-locked_loop)
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* PM - Platform Management
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@ -843,7 +843,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
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Segment:Offset index pair. In 2022, this is still the mode that
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x86-64 processors are in at the reset vector!
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* RDMA - [**Remote Direct Memory
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Access**](http://en.wikipedia.org/wiki/Remote_Direct_Memory_Access) is
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Access**](https://en.wikipedia.org/wiki/Remote_Direct_Memory_Access) is
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a concept whereby two or more computers communicate via DMA directly
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from main memory of one system to the main memory of another.
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* RFC - Request for Comment
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@ -962,7 +962,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
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* SO-DIMM: Small Outline Dual In-Line Memory Module
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* SoC - System on a Chip
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* SOIC - [**Small-Outline Integrated
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Circuit**](http://en.wikipedia.org/wiki/Small-outline_integrated_circuit)
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Circuit**](https://en.wikipedia.org/wiki/Small-outline_integrated_circuit)
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* SPD - [**Serial Presence
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Detect**](https://en.wikipedia.org/wiki/Serial_presence_detect)
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* SPI - [**Serial Peripheral
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