- Remove e7501 root_complex
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1773 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
parent
52c2277a1b
commit
ab49946a56
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@ -8,8 +8,186 @@
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#include <bitops.h>
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#include "chip.h"
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#if CONFIG_CHIP_NAME
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#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
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static void pci_domain_read_resources(device_t dev)
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{
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struct resource *resource;
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unsigned reg;
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/* Initialize the system wide io space constraints */
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resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
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resource->limit = 0xffffUL;
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resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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/* Initialize the system wide memory resources constraints */
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resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
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resource->limit = 0xffffffffULL;
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resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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}
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static void ram_resource(device_t dev, unsigned long index,
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unsigned long basek, unsigned long sizek)
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{
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struct resource *resource;
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if (!sizek) {
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return;
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}
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resource = new_resource(dev, index);
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resource->base = ((resource_t)basek) << 10;
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resource->size = ((resource_t)sizek) << 10;
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resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
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IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
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}
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static void tolm_test(void *gp, struct device *dev, struct resource *new)
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{
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struct resource **best_p = gp;
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struct resource *best;
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best = *best_p;
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if (!best || (best->base > new->base)) {
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best = new;
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}
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*best_p = best;
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}
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static uint32_t find_pci_tolm(struct bus *bus)
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{
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struct resource *min;
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uint32_t tolm;
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min = 0;
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search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
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tolm = 0xffffffffUL;
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if (min && tolm > min->base) {
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tolm = min->base;
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}
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return tolm;
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}
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static void pci_domain_set_resources(device_t dev)
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{
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struct resource *resource, *last;
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device_t mc_dev;
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uint32_t pci_tolm;
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pci_tolm = find_pci_tolm(&dev->link[0]);
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mc_dev = dev->link[0].children;
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if (mc_dev) {
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/* Figure out which areas are/should be occupied by RAM.
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* This is all computed in kilobytes and converted to/from
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* the memory controller right at the edges.
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* Having different variables in different units is
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* too confusing to get right. Kilobytes are good up to
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* 4 Terabytes of RAM...
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*/
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uint16_t tolm_r, remapbase_r, remaplimit_r;
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unsigned long tomk, tolmk;
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unsigned long remapbasek, remaplimitk;
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int idx;
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/* Get the value of the highest DRB. This tells the end of
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* the physical memory. The units are ticks of 64MB
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* i.e. 1 means 64MB.
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*/
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tomk = ((unsigned long)pci_read_config8(mc_dev, 0x67)) << 16;
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/* Compute the top of Low memory */
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tolmk = pci_tolm >> 10;
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if (tolmk >= tomk) {
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/* The PCI hole does not overlap memory
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* we won't use the remap window.
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*/
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tolmk = tomk;
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remapbasek = 0x3ff << 16;
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remaplimitk = 0 << 16;
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}
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else {
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/* The PCI memory hole overlaps memory
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* setup the remap window.
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*/
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/* Find the bottom of the remap window
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* is it above 4G?
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*/
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remapbasek = 4*1024*1024;
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if (tomk > remapbasek) {
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remapbasek = tomk;
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}
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/* Find the limit of the remap window */
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remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
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}
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/* Write the ram configuration registers,
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* preserving the reserved bits.
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*/
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tolm_r = pci_read_config16(mc_dev, 0xc4);
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tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
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pci_write_config16(mc_dev, 0xc4, tolm_r);
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remapbase_r = pci_read_config16(mc_dev, 0xc6);
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remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
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pci_write_config16(mc_dev, 0xc6, remapbase_r);
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remaplimit_r = pci_read_config16(mc_dev, 0xc8);
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remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
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pci_write_config16(mc_dev, 0xc8, remaplimit_r);
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/* Report the memory regions */
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idx = 10;
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ram_resource(dev, idx++, 0, 640);
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ram_resource(dev, idx++, 768, tolmk - 768);
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if (tomk > 4*1024*1024) {
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ram_resource(dev, idx++, 4096*1024, tomk - 4*1024*1024);
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}
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if (remaplimitk >= remapbasek) {
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ram_resource(dev, idx++, remapbasek,
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(remaplimitk + 64*1024) - remapbasek);
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}
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}
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assign_resources(&dev->link[0]);
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}
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static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
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{
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max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
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return max;
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}
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static struct device_operations pci_domain_ops = {
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.read_resources = pci_domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.enable_resources = enable_childrens_resources,
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.init = 0,
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.scan_bus = pci_domain_scan_bus,
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};
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static void cpu_bus_init(device_t dev)
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{
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initialize_cpus(&dev->link[0]);
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}
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static void cpu_bus_noop(device_t dev)
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{
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}
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static struct device_operations cpu_bus_ops = {
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.read_resources = cpu_bus_noop,
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.set_resources = cpu_bus_noop,
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.enable_resources = cpu_bus_noop,
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.init = cpu_bus_init,
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.scan_bus = 0,
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};
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static void enable_dev(struct device *dev)
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{
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
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dev->ops = &pci_domain_ops;
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pci_set_method_conf1();
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}
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else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
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dev->ops = &cpu_bus_ops;
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}
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}
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struct chip_operations northbridge_intel_e7501_ops = {
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CHIP_NAME("Intel E7501 northbridge")
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};
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#endif
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@ -1,2 +0,0 @@
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config chip.h
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object root_complex.o
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@ -1,5 +0,0 @@
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struct northbridge_intel_e7501_root_complex_config
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{
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};
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extern struct chip_operations northbridge_intel_e7501_root_complex_ops;
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@ -1,193 +0,0 @@
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#include <console/console.h>
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#include <arch/io.h>
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#include <stdint.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <stdlib.h>
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#include <string.h>
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#include <bitops.h>
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#include "chip.h"
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#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
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static void pci_domain_read_resources(device_t dev)
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{
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struct resource *resource;
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unsigned reg;
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/* Initialize the system wide io space constraints */
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resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
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resource->limit = 0xffffUL;
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resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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/* Initialize the system wide memory resources constraints */
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resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
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resource->limit = 0xffffffffULL;
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resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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}
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static void ram_resource(device_t dev, unsigned long index,
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unsigned long basek, unsigned long sizek)
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{
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struct resource *resource;
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if (!sizek) {
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return;
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}
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resource = new_resource(dev, index);
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resource->base = ((resource_t)basek) << 10;
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resource->size = ((resource_t)sizek) << 10;
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resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
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IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
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}
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static void tolm_test(void *gp, struct device *dev, struct resource *new)
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{
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struct resource **best_p = gp;
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struct resource *best;
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best = *best_p;
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if (!best || (best->base > new->base)) {
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best = new;
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}
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*best_p = best;
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}
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static uint32_t find_pci_tolm(struct bus *bus)
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{
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struct resource *min;
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uint32_t tolm;
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min = 0;
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search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
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tolm = 0xffffffffUL;
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if (min && tolm > min->base) {
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tolm = min->base;
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}
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return tolm;
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}
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static void pci_domain_set_resources(device_t dev)
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{
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struct resource *resource, *last;
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device_t mc_dev;
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uint32_t pci_tolm;
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pci_tolm = find_pci_tolm(&dev->link[0]);
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mc_dev = dev->link[0].children;
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if (mc_dev) {
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/* Figure out which areas are/should be occupied by RAM.
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* This is all computed in kilobytes and converted to/from
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* the memory controller right at the edges.
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* Having different variables in different units is
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* too confusing to get right. Kilobytes are good up to
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* 4 Terabytes of RAM...
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*/
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uint16_t tolm_r, remapbase_r, remaplimit_r;
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unsigned long tomk, tolmk;
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unsigned long remapbasek, remaplimitk;
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int idx;
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/* Get the value of the highest DRB. This tells the end of
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* the physical memory. The units are ticks of 64MB
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* i.e. 1 means 64MB.
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*/
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tomk = ((unsigned long)pci_read_config8(mc_dev, 0x67)) << 16;
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/* Compute the top of Low memory */
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tolmk = pci_tolm >> 10;
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if (tolmk >= tomk) {
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/* The PCI hole does not overlap memory
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* we won't use the remap window.
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*/
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tolmk = tomk;
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remapbasek = 0x3ff << 16;
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remaplimitk = 0 << 16;
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}
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else {
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/* The PCI memory hole overlaps memory
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* setup the remap window.
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*/
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/* Find the bottom of the remap window
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* is it above 4G?
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*/
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remapbasek = 4*1024*1024;
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if (tomk > remapbasek) {
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remapbasek = tomk;
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}
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/* Find the limit of the remap window */
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remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
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}
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/* Write the ram configuration registers,
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* preserving the reserved bits.
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*/
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tolm_r = pci_read_config16(mc_dev, 0xc4);
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tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
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pci_write_config16(mc_dev, 0xc4, tolm_r);
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remapbase_r = pci_read_config16(mc_dev, 0xc6);
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remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
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pci_write_config16(mc_dev, 0xc6, remapbase_r);
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remaplimit_r = pci_read_config16(mc_dev, 0xc8);
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remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
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pci_write_config16(mc_dev, 0xc8, remaplimit_r);
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/* Report the memory regions */
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idx = 10;
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ram_resource(dev, idx++, 0, 640);
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ram_resource(dev, idx++, 768, tolmk - 768);
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if (tomk > 4*1024*1024) {
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ram_resource(dev, idx++, 4096*1024, tomk - 4*1024*1024);
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}
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if (remaplimitk >= remapbasek) {
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ram_resource(dev, idx++, remapbasek,
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(remaplimitk + 64*1024) - remapbasek);
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}
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}
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assign_resources(&dev->link[0]);
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}
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static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
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{
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max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
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return max;
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}
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static struct device_operations pci_domain_ops = {
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.read_resources = pci_domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.enable_resources = enable_childrens_resources,
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.init = 0,
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.scan_bus = pci_domain_scan_bus,
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};
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static void cpu_bus_init(device_t dev)
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{
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initialize_cpus(&dev->link[0]);
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}
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static void cpu_bus_noop(device_t dev)
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{
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}
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static struct device_operations cpu_bus_ops = {
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.read_resources = cpu_bus_noop,
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.set_resources = cpu_bus_noop,
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.enable_resources = cpu_bus_noop,
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.init = cpu_bus_init,
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.scan_bus = 0,
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};
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static void enable_dev(struct device *dev)
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{
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
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dev->ops = &pci_domain_ops;
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pci_set_method_conf1();
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}
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else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
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dev->ops = &cpu_bus_ops;
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}
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}
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struct chip_operations northbridge_intel_e7501_root_complex_ops = {
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CHIP_NAME("Intel E7501 Root Complex")
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.enable_dev = enable_dev,
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};
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