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mb/google/brya/var/crota: Limit dram speed to 4800 MT/s 

When using LPDDR5 on a Type-C PCB, the Intel ADL-P PDG (Rev. 2.0.1)
page 121 recommends a maximum DRAM speed of 4800 MT/s.

BUG=b:229549930
BRANCH=none
TEST=build and pass memory training

Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I38f0006d478702afb382d30338f20b46641964ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Scott Chao 2022-04-18 11:11:46 +08:00 committed by Felix Held
parent 075f4e7751
commit ab58d2b488
1 changed files with 2 additions and 0 deletions
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src/mainboard/google/brya/variants/crota/overridetree.cb
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@ -19,6 +19,8 @@ end
chip soc/intel/alderlake chip soc/intel/alderlake
register "max_dram_speed" = "4800"
# Acoustic settings # Acoustic settings
register "acoustic_noise_mitigation" = "1" register "acoustic_noise_mitigation" = "1"
register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_4" register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_4"