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soc/intel/common/block/pmc: Add helper routines to read/write PM1_CNT 

This change adds and uses helper routines for reading and writing
PM1_CNT register.

BUG=b:67874513

Change-Id: I69b9347ab54a392b67ba733eb00922583dc1ee5f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22081
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Furquan Shaikh 2017-10-16 22:19:13 -07:00 committed by Furquan Shaikh
parent e48fb54b16
commit ab6201835a
2 changed files with 24 additions and 9 deletions
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3
src/soc/intel/common/block/include/intelblocks/pmclib.h
View File

@ -47,6 +47,9 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps,
void pmc_update_pm1_enable(uint16_t events);
uint16_t pmc_read_pm1_enable(void);
uint32_t pmc_read_pm1_control(void);
void pmc_write_pm1_control(uint32_t pm1_cnt);
/*
* Function to print, clear, and return SMI status bits in SMI_STS
* register. This function internally calls pmc_reset_smi_status with

30
src/soc/intel/common/block/pmc/pmclib.c
View File

@ -155,18 +155,28 @@ void pmc_enable_pm1(uint16_t events)
outw(events, ACPI_BASE_ADDRESS + PM1_EN);
}
uint32_t pmc_read_pm1_control(void)
{
return inl(ACPI_BASE_ADDRESS + PM1_CNT);
}
void pmc_write_pm1_control(uint32_t pm1_cnt)
{
outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
}
void pmc_enable_pm1_control(uint32_t mask)
{
uint32_t pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
uint32_t pm1_cnt = pmc_read_pm1_control();
pm1_cnt |= mask;
outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
pmc_write_pm1_control(pm1_cnt);
}
void pmc_disable_pm1_control(uint32_t mask)
{
uint32_t pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
uint32_t pm1_cnt = pmc_read_pm1_control();
pm1_cnt &= ~mask;
outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
pmc_write_pm1_control(pm1_cnt);
}
static uint16_t reset_pm1_status(void)
@ -357,7 +367,7 @@ static int pmc_prev_sleep_state(const struct chipset_power_state *ps)
}
/* Clear SLP_TYP. */
outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
pmc_write_pm1_control(ps->pm1_cnt & ~(SLP_TYP));
}
return soc_prev_sleep_state(ps, prev_sleep_state);
}
@ -394,7 +404,7 @@ void pmc_fill_pm_reg_info(struct chipset_power_state *ps)
ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
ps->pm1_cnt = pmc_read_pm1_control();
printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
ps->pm1_sts, ps->pm1_en, ps->pm1_cnt);
@ -470,7 +480,7 @@ int vboot_platform_is_resuming(void)
if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS))
return 0;
return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3;
return acpi_sleep_from_pm1(pmc_read_pm1_control()) == ACPI_S3;
}
/* Read and clear GPE status (defined in arch/acpi.h) */
@ -512,8 +522,10 @@ int acpi_get_gpe(int gpe)
*/
void vboot_platform_prepare_reboot(void)
{
const uint16_t port = ACPI_BASE_ADDRESS + PM1_CNT;
outl((inl(port) & ~(SLP_TYP)) | (SLP_TYP_S5 << SLP_TYP_SHIFT), port);
uint32_t pm1_cnt;
pm1_cnt = (pmc_read_pm1_control() & ~(SLP_TYP)) |
(SLP_TYP_S5 << SLP_TYP_SHIFT);
pmc_write_pm1_control(pm1_cnt);
}
void poweroff(void)