soc/intel/common/block/pmc: Add helper routines to read/write PM1_CNT
This change adds and uses helper routines for reading and writing PM1_CNT register. BUG=b:67874513 Change-Id: I69b9347ab54a392b67ba733eb00922583dc1ee5f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22081 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -47,6 +47,9 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps,
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void pmc_update_pm1_enable(uint16_t events);
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void pmc_update_pm1_enable(uint16_t events);
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uint16_t pmc_read_pm1_enable(void);
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uint16_t pmc_read_pm1_enable(void);
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uint32_t pmc_read_pm1_control(void);
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void pmc_write_pm1_control(uint32_t pm1_cnt);
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/*
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/*
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* Function to print, clear, and return SMI status bits in SMI_STS
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* Function to print, clear, and return SMI status bits in SMI_STS
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* register. This function internally calls pmc_reset_smi_status with
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* register. This function internally calls pmc_reset_smi_status with
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@ -155,18 +155,28 @@ void pmc_enable_pm1(uint16_t events)
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outw(events, ACPI_BASE_ADDRESS + PM1_EN);
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outw(events, ACPI_BASE_ADDRESS + PM1_EN);
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}
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}
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uint32_t pmc_read_pm1_control(void)
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{
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return inl(ACPI_BASE_ADDRESS + PM1_CNT);
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}
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void pmc_write_pm1_control(uint32_t pm1_cnt)
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{
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outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
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}
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void pmc_enable_pm1_control(uint32_t mask)
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void pmc_enable_pm1_control(uint32_t mask)
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{
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{
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uint32_t pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
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uint32_t pm1_cnt = pmc_read_pm1_control();
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pm1_cnt |= mask;
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pm1_cnt |= mask;
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outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
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pmc_write_pm1_control(pm1_cnt);
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}
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}
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void pmc_disable_pm1_control(uint32_t mask)
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void pmc_disable_pm1_control(uint32_t mask)
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{
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{
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uint32_t pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
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uint32_t pm1_cnt = pmc_read_pm1_control();
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pm1_cnt &= ~mask;
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pm1_cnt &= ~mask;
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outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
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pmc_write_pm1_control(pm1_cnt);
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}
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}
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static uint16_t reset_pm1_status(void)
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static uint16_t reset_pm1_status(void)
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@ -357,7 +367,7 @@ static int pmc_prev_sleep_state(const struct chipset_power_state *ps)
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}
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}
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/* Clear SLP_TYP. */
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/* Clear SLP_TYP. */
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outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
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pmc_write_pm1_control(ps->pm1_cnt & ~(SLP_TYP));
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}
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}
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return soc_prev_sleep_state(ps, prev_sleep_state);
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return soc_prev_sleep_state(ps, prev_sleep_state);
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}
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}
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@ -394,7 +404,7 @@ void pmc_fill_pm_reg_info(struct chipset_power_state *ps)
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ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
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ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
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ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
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ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
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ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
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ps->pm1_cnt = pmc_read_pm1_control();
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printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
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printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
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ps->pm1_sts, ps->pm1_en, ps->pm1_cnt);
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ps->pm1_sts, ps->pm1_en, ps->pm1_cnt);
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@ -470,7 +480,7 @@ int vboot_platform_is_resuming(void)
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if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS))
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if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS))
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return 0;
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return 0;
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return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3;
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return acpi_sleep_from_pm1(pmc_read_pm1_control()) == ACPI_S3;
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}
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}
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/* Read and clear GPE status (defined in arch/acpi.h) */
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/* Read and clear GPE status (defined in arch/acpi.h) */
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@ -512,8 +522,10 @@ int acpi_get_gpe(int gpe)
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*/
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*/
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void vboot_platform_prepare_reboot(void)
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void vboot_platform_prepare_reboot(void)
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{
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{
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const uint16_t port = ACPI_BASE_ADDRESS + PM1_CNT;
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uint32_t pm1_cnt;
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outl((inl(port) & ~(SLP_TYP)) | (SLP_TYP_S5 << SLP_TYP_SHIFT), port);
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pm1_cnt = (pmc_read_pm1_control() & ~(SLP_TYP)) |
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(SLP_TYP_S5 << SLP_TYP_SHIFT);
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pmc_write_pm1_control(pm1_cnt);
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}
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}
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void poweroff(void)
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void poweroff(void)
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