soc/intel/adl/chip.h: Rename max_dram_speed to include units
The unit of dram speed is MT/s so append it on variable name. BUG=b:229549930 BRANCH=none TEST=build coreboot without error Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I83c780440613050c0202f95d5f64991b61d9c280 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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@ -19,7 +19,7 @@ end
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chip soc/intel/alderlake
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register "max_dram_speed" = "4800"
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register "max_dram_speed_mts" = "4800"
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# Acoustic settings
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register "acoustic_noise_mitigation" = "1"
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@ -24,7 +24,7 @@ end
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chip soc/intel/alderlake
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register "sagv" = "SaGv_Enabled"
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register "max_dram_speed" = "3733"
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register "max_dram_speed_mts" = "3733"
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# Acoustic settings
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register "acoustic_noise_mitigation" = "1"
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@ -24,7 +24,7 @@ end
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chip soc/intel/alderlake
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register "sagv" = "SaGv_Enabled"
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register "max_dram_speed" = "3733"
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register "max_dram_speed_mts" = "3733"
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# Acoustic settings
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register "acoustic_noise_mitigation" = "1"
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@ -484,7 +484,7 @@ struct soc_intel_alderlake_config {
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*/
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struct vr_config domain_vr_config[NUM_VR_DOMAINS];
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uint16_t max_dram_speed;
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uint16_t max_dram_speed_mts;
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enum {
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SLP_S3_ASSERTION_DEFAULT,
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@ -141,8 +141,8 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg,
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{
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m_cfg->SaGv = config->sagv;
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m_cfg->RMT = config->RMT;
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if (config->max_dram_speed)
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m_cfg->DdrFreqLimit = config->max_dram_speed;
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if (config->max_dram_speed_mts)
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m_cfg->DdrFreqLimit = config->max_dram_speed_mts;
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}
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static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg,
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