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soc/intel/adl/chip.h: Rename max_dram_speed to include units 

The unit of dram speed is MT/s so append it on variable name.

BUG=b:229549930
BRANCH=none
TEST=build coreboot without error

Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I83c780440613050c0202f95d5f64991b61d9c280
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Scott Chao 2022-04-20 15:16:06 +08:00 committed by Felix Held
parent 0ed3dfc92a
commit ab638c17e2
5 changed files with 6 additions and 6 deletions
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2
src/mainboard/google/brya/variants/crota/overridetree.cb
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@ -19,7 +19,7 @@ end
chip soc/intel/alderlake chip soc/intel/alderlake
register "max_dram_speed" = "4800" register "max_dram_speed_mts" = "4800"
# Acoustic settings # Acoustic settings
register "acoustic_noise_mitigation" = "1" register "acoustic_noise_mitigation" = "1"

2
src/mainboard/google/brya/variants/primus/overridetree.cb
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@ -24,7 +24,7 @@ end
chip soc/intel/alderlake chip soc/intel/alderlake
register "sagv" = "SaGv_Enabled" register "sagv" = "SaGv_Enabled"
register "max_dram_speed" = "3733" register "max_dram_speed_mts" = "3733"
# Acoustic settings # Acoustic settings
register "acoustic_noise_mitigation" = "1" register "acoustic_noise_mitigation" = "1"

2
src/mainboard/google/brya/variants/primus4es/overridetree.cb
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@ -24,7 +24,7 @@ end
chip soc/intel/alderlake chip soc/intel/alderlake
register "sagv" = "SaGv_Enabled" register "sagv" = "SaGv_Enabled"
register "max_dram_speed" = "3733" register "max_dram_speed_mts" = "3733"
# Acoustic settings # Acoustic settings
register "acoustic_noise_mitigation" = "1" register "acoustic_noise_mitigation" = "1"

2
src/soc/intel/alderlake/chip.h
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@ -484,7 +484,7 @@ struct soc_intel_alderlake_config {
*/ */
struct vr_config domain_vr_config[NUM_VR_DOMAINS]; struct vr_config domain_vr_config[NUM_VR_DOMAINS];
uint16_t max_dram_speed; uint16_t max_dram_speed_mts;
enum { enum {
SLP_S3_ASSERTION_DEFAULT, SLP_S3_ASSERTION_DEFAULT,

4
src/soc/intel/alderlake/romstage/fsp_params.c
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@ -141,8 +141,8 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg,
{ {
m_cfg->SaGv = config->sagv; m_cfg->SaGv = config->sagv;
m_cfg->RMT = config->RMT; m_cfg->RMT = config->RMT;
if (config->max_dram_speed) if (config->max_dram_speed_mts)
m_cfg->DdrFreqLimit = config->max_dram_speed; m_cfg->DdrFreqLimit = config->max_dram_speed_mts;
} }
static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg, static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg,