GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/amd/picasso/sb: Gate FCH AL2AHB clocks 

Gate the A-Link to AHB Bridge clocks to save power. These
are internal clocks and are unneeded for Raven/Picasso.
This was previously performed within the AGESA FSP but this
change relocates it into coreboot.

BUG=b:154144239
TEST=Check AL2AHB clock gate bits at the end of POST before and
after change with HDT.

Change-Id: Ifcbc144a8769f8ea440cdd560bab146bf5058cf9
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Matt Papageorge 2020-06-26 08:47:00 -05:00 committed by Furquan Shaikh
parent 9857c90685
commit ab83b43b34
2 changed files with 23 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/soc/amd/picasso/include/soc/iomap.h
View File

@ -12,7 +12,12 @@
#endif #endif
#define HPET_BASE_ADDRESS 0xfed00000 #define HPET_BASE_ADDRESS 0xfed00000
/* FCH AL2AHB Registers */
#define ALINK_AHB_ADDRESS 0xfedc0000 #define ALINK_AHB_ADDRESS 0xfedc0000
#define AL2AHB_CONTROL_CLK_OFFSET 0x10
#define AL2AHB_CLK_GATE_EN (1 << 1)
#define AL2AHB_CONTROL_HCLK_OFFSET 0x30
#define AL2AHB_HCLK_GATE_EN (1 << 1)
/* Reserved 0xfecd1000-0xfedc3fff */ /* Reserved 0xfecd1000-0xfedc3fff */

18
src/soc/amd/picasso/southbridge.c
View File

@ -328,11 +328,29 @@ static void set_nvs_sws(void *unused)
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL); BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL);
/*
* A-Link to AHB bridge, part of the AMBA fabric. These are internal clocks
* and unneeded for Raven/Picasso so gate them to save power.
*/
static void al2ahb_clock_gate(void)
{
uint8_t al2ahb_val;
uintptr_t al2ahb_base = ALINK_AHB_ADDRESS;
al2ahb_val = read8((void *)(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET));
al2ahb_val |= AL2AHB_CLK_GATE_EN;
write8((void *)(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET), al2ahb_val);
al2ahb_val = read8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET));
al2ahb_val |= AL2AHB_HCLK_GATE_EN;
write8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET), al2ahb_val);
}
void southbridge_init(void *chip_info) void southbridge_init(void *chip_info)
{ {
i2c_soc_init(); i2c_soc_init();
sb_init_acpi_ports(); sb_init_acpi_ports();
acpi_clear_pm1_status(); acpi_clear_pm1_status();
al2ahb_clock_gate();
} }
static void set_sb_final_nvs(void) static void set_sb_final_nvs(void)