soc/amd/picasso/sb: Gate FCH AL2AHB clocks
Gate the A-Link to AHB Bridge clocks to save power. These are internal clocks and are unneeded for Raven/Picasso. This was previously performed within the AGESA FSP but this change relocates it into coreboot. BUG=b:154144239 TEST=Check AL2AHB clock gate bits at the end of POST before and after change with HDT. Change-Id: Ifcbc144a8769f8ea440cdd560bab146bf5058cf9 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -12,7 +12,12 @@
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#endif
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#define HPET_BASE_ADDRESS 0xfed00000
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/* FCH AL2AHB Registers */
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#define ALINK_AHB_ADDRESS 0xfedc0000
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#define AL2AHB_CONTROL_CLK_OFFSET 0x10
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#define AL2AHB_CLK_GATE_EN (1 << 1)
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#define AL2AHB_CONTROL_HCLK_OFFSET 0x30
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#define AL2AHB_HCLK_GATE_EN (1 << 1)
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/* Reserved 0xfecd1000-0xfedc3fff */
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@ -328,11 +328,29 @@ static void set_nvs_sws(void *unused)
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BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL);
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/*
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* A-Link to AHB bridge, part of the AMBA fabric. These are internal clocks
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* and unneeded for Raven/Picasso so gate them to save power.
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*/
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static void al2ahb_clock_gate(void)
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{
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uint8_t al2ahb_val;
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uintptr_t al2ahb_base = ALINK_AHB_ADDRESS;
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al2ahb_val = read8((void *)(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET));
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al2ahb_val |= AL2AHB_CLK_GATE_EN;
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write8((void *)(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET), al2ahb_val);
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al2ahb_val = read8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET));
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al2ahb_val |= AL2AHB_HCLK_GATE_EN;
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write8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET), al2ahb_val);
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}
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void southbridge_init(void *chip_info)
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{
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i2c_soc_init();
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sb_init_acpi_ports();
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acpi_clear_pm1_status();
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al2ahb_clock_gate();
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}
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static void set_sb_final_nvs(void)
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