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i82801gx: Handle whole FADT in southbridge. 

Do all the handling in SB code with few parameters from devicetree.cb
instead of having mobo callbacks.

Change-Id: I8fd02ff05553a3c51ea5f6ae66b8f5502509e2bc
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7199
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Vladimir Serbinenko 2014-10-25 15:18:25 +02:00
parent 9c4f1b8e05
commit ab83ef02c7
20 changed files with 60 additions and 253 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/arch/x86/boot/acpi.c
View File

@ -660,7 +660,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs, void *dsdt)
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
header->length = sizeof(acpi_fadt_t);
header->revision = 3;
header->revision = 4;
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
memcpy(header->asl_compiler_id, ASLC, 4);
@ -680,8 +680,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs, void *dsdt)
fadt->preferred_pm_profile = PM_DESKTOP;
}
southbridge_fill_fadt(fadt);
mainboard_fill_fadt(fadt);
acpi_fill_fadt(fadt);
header->checksum =
acpi_checksum((void *) fadt, header->length);

3
src/arch/x86/include/arch/acpi.h
View File

@ -495,8 +495,7 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current,
void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id);
void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs, void *dsdt);
#if IS_ENABLED(CONFIG_COMMON_FADT)
void southbridge_fill_fadt(acpi_fadt_t * fadt);
void mainboard_fill_fadt(acpi_fadt_t * fadt);
void acpi_fill_fadt(acpi_fadt_t * fadt);
#endif
void update_ssdt(void *ssdt);

4
src/mainboard/apple/macbook21/devicetree.cb
View File

@ -70,6 +70,10 @@ chip northbridge/intel/i945
register "ide_enable_secondary" = "1"
register "c4onc3_enable" = "1"
register "c3_latency" = "0x23"
register "p_cnt_throttling_supported" = "1"
device pci 1b.0 on # Audio Controller
subsystemid 0x8384 0x7680
end

27
src/mainboard/apple/macbook21/fadt.c
View File

@ -1,27 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <arch/acpi.h>
void mainboard_fill_fadt(acpi_fadt_t * fadt)
{
fadt->p_lvl3_lat = 0x23;
}

4
src/mainboard/getac/p470/devicetree.cb
View File

@ -60,6 +60,10 @@ chip northbridge/intel/i945
register "ide_enable_secondary" = "0x0"
register "sata_ahci" = "0x0"
register "c3_latency" = "85"
register "docking_supported" = "1"
register "p_cnt_throttling_supported" = "1"
device pci 1b.0 on end # High Definition Audio
device pci 1c.0 on end # PCIe port 1
device pci 1c.1 on end # PCIe port 2

28
src/mainboard/getac/p470/fadt.c
View File

@ -1,28 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <arch/acpi.h>
void mainboard_fill_fadt(acpi_fadt_t * fadt)
{
fadt->p_lvl3_lat = 85;
fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
}

3
src/mainboard/ibase/mb899/devicetree.cb
View File

@ -32,6 +32,9 @@ chip northbridge/intel/i945
register "ide_enable_secondary" = "0x0"
register "sata_ahci" = "0x1"
register "c3_latency" = "85"
register "p_cnt_throttling_supported" = "0"
#device pci 1b.0 on end # High Definition Audio
device pci 1c.0 on end # PCIe
device pci 1c.1 on end # PCIe

32
src/mainboard/ibase/mb899/fadt.c
View File

@ -1,32 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <string.h>
#include <device/pci.h>
#include <arch/acpi.h>
#include <cpu/x86/smm.h>
void mainboard_fill_fadt(acpi_fadt_t * fadt)
{
fadt->p_lvl3_lat = 85;
fadt->duty_width = 0;
fadt->iapc_boot_arch = 0x03;
fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_PLATFORM_CLOCK;
}

2
src/mainboard/intel/d945gclf/devicetree.cb
View File

@ -53,6 +53,8 @@ chip northbridge/intel/i945
register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x0"
register "sata_ahci" = "0x0"
register "c3_latency" = "85"
register "p_cnt_throttling_supported" = "0"
device pci 1b.0 on end # High Definition Audio
device pci 1c.0 on end # PCIe

28
src/mainboard/intel/d945gclf/fadt.c
View File

@ -1,28 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/acpi.h>
void mainboard_fill_fadt(acpi_fadt_t * fadt)
{
fadt->p_lvl3_lat = 85;
fadt->duty_width = 0;
fadt->iapc_boot_arch = 0x03;
fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_PLATFORM_CLOCK;
}

2
src/mainboard/kontron/986lcd-m/devicetree.cb
View File

@ -32,6 +32,8 @@ chip northbridge/intel/i945
register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x1"
register "sata_ahci" = "0x0"
register "c3_latency" = "85"
register "p_cnt_throttling_supported" = "0"
device pci 1b.0 on end # High Definition Audio
device pci 1c.0 on end # PCIe

33
src/mainboard/kontron/986lcd-m/fadt.c
View File

@ -1,33 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <string.h>
#include <device/pci.h>
#include <arch/acpi.h>
#include <cpu/x86/smm.h>
void mainboard_fill_fadt(acpi_fadt_t * fadt)
{
fadt->p_lvl3_lat = 85;
fadt->duty_width = 0;
fadt->iapc_boot_arch = 0x03;
fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED
| ACPI_FADT_RESET_REGISTER |ACPI_FADT_PLATFORM_CLOCK;
}

3
src/mainboard/lenovo/t60/devicetree.cb
View File

@ -70,6 +70,9 @@ chip northbridge/intel/i945
register "alt_gp_smi_en" = "0x1000"
register "c4onc3_enable" = "1"
register "c3_latency" = "0x23"
register "docking_supported" = "1"
register "p_cnt_throttling_supported" = "1"
device pci 1b.0 on # Audio Controller
subsystemid 0x17aa 0x2010

28
src/mainboard/lenovo/t60/fadt.c
View File

@ -1,28 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <arch/acpi.h>
void mainboard_fill_fadt(acpi_fadt_t * fadt)
{
fadt->p_lvl3_lat = 0x23;
fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
}

5
src/mainboard/lenovo/x60/devicetree.cb
View File

@ -68,6 +68,11 @@ chip northbridge/intel/i945
register "alt_gp_smi_en" = "0x1000"
register "c4onc3_enable" = "1"
register "c3_latency" = "0x23"
register "docking_supported" = "1"
register "p_cnt_throttling_supported" = "1"
device pci 1b.0 on # Audio Controller
subsystemid 0x17aa 0x2010
end

28
src/mainboard/lenovo/x60/fadt.c
View File

@ -1,28 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <arch/acpi.h>
void mainboard_fill_fadt(acpi_fadt_t * fadt)
{
fadt->p_lvl3_lat = 0x23;
fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
}

4
src/mainboard/roda/rk886ex/devicetree.cb
View File

@ -54,6 +54,10 @@ chip northbridge/intel/i945
register "gpi7_routing" = "2"
register "gpe0_en" = "0x20800007"
register "c3_latency" = "0x23"
register "docking_supported" = "1"
register "p_cnt_throttling_supported" = "1"
register "ide_legacy_combined" = "0x1"
register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x0"

28
src/mainboard/roda/rk886ex/fadt.c
View File

@ -1,28 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <arch/acpi.h>
void mainboard_fill_fadt(acpi_fadt_t * fadt)
{
fadt->p_lvl3_lat = 0x23;
fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
}

3
src/southbridge/intel/i82801gx/chip.h
View File

@ -71,6 +71,9 @@ struct southbridge_intel_i82801gx_config {
uint32_t sata_ports_implemented;
int c4onc3_enable:1;
int docking_supported:1;
int p_cnt_throttling_supported:1;
int c3_latency;
};
#endif /* SOUTHBRIDGE_INTEL_I82801GX_CHIP_H */

43
src/southbridge/intel/i82801gx/lpc.c
View File

@ -455,9 +455,11 @@ static void lpc_init(struct device *dev)
i82801gx_fixups(dev);
}
void southbridge_fill_fadt(acpi_fadt_t * fadt)
void acpi_fill_fadt(acpi_fadt_t * fadt)
{
u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
config_t *chip = dev->chip_info;
u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
fadt->pm1a_evt_blk = pmbase;
fadt->pm1b_evt_blk = 0x0;
@ -479,7 +481,7 @@ void southbridge_fill_fadt(acpi_fadt_t * fadt)
fadt->reset_reg.space_id = 1;
fadt->reset_reg.bit_width = 8;
fadt->reset_reg.bit_offset = 0;
fadt->reset_reg.resv = 0;
fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
fadt->reset_reg.addrl = 0xcf9;
fadt->reset_reg.addrh = 0;
@ -488,56 +490,56 @@ void southbridge_fill_fadt(acpi_fadt_t * fadt)
fadt->x_pm1a_evt_blk.space_id = 1;
fadt->x_pm1a_evt_blk.bit_width = 32;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.resv = 0;
fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
fadt->x_pm1a_evt_blk.addrl = pmbase;
fadt->x_pm1a_evt_blk.addrh = 0x0;
fadt->x_pm1b_evt_blk.space_id = 0;
fadt->x_pm1b_evt_blk.bit_width = 0;
fadt->x_pm1b_evt_blk.bit_offset = 0;
fadt->x_pm1b_evt_blk.resv = 0;
fadt->x_pm1b_evt_blk.access_size = 0;
fadt->x_pm1b_evt_blk.addrl = 0x0;
fadt->x_pm1b_evt_blk.addrh = 0x0;
fadt->x_pm1a_cnt_blk.space_id = 1;
fadt->x_pm1a_cnt_blk.bit_width = 16;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.resv = 0;
fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm1b_cnt_blk.space_id = 0;
fadt->x_pm1b_cnt_blk.bit_width = 0;
fadt->x_pm1b_cnt_blk.bit_offset = 0;
fadt->x_pm1b_cnt_blk.resv = 0;
fadt->x_pm1b_cnt_blk.access_size = 0;
fadt->x_pm1b_cnt_blk.addrl = 0x0;
fadt->x_pm1b_cnt_blk.addrh = 0x0;
fadt->x_pm2_cnt_blk.space_id = 1;
fadt->x_pm2_cnt_blk.bit_width = 8;
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.resv = 0;
fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
fadt->x_pm2_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.resv = 0;
fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = 1;
fadt->x_gpe0_blk.bit_width = 64;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.resv = 0;
fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
fadt->x_gpe0_blk.addrl = pmbase + 0x28;
fadt->x_gpe0_blk.addrh = 0x0;
fadt->x_gpe1_blk.space_id = 0;
fadt->x_gpe1_blk.bit_width = 0;
fadt->x_gpe1_blk.bit_offset = 0;
fadt->x_gpe1_blk.resv = 0;
fadt->x_gpe1_blk.access_size = 0;
fadt->x_gpe1_blk.addrl = 0x0;
fadt->x_gpe1_blk.addrh = 0x0;
fadt->day_alrm = 0xd;
@ -554,14 +556,23 @@ void southbridge_fill_fadt(acpi_fadt_t * fadt)
fadt->cst_cnt = APM_CNT_CST_CONTROL;
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = 0x23;
fadt->p_lvl3_lat = chip->c3_latency;
fadt->flush_size = 0;
fadt->flush_stride = 0;
fadt->duty_offset = 1;
fadt->duty_width = 3;
fadt->iapc_boot_arch = 0x00;
fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE;
if (chip->p_cnt_throttling_supported) {
fadt->duty_width = 3;
} else {
fadt->duty_width = 0;
}
fadt->iapc_boot_arch = 0x03;
fadt->flags = (ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED
| ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE
| ACPI_FADT_PLATFORM_CLOCK | ACPI_FADT_RESET_REGISTER
| ACPI_FADT_C2_MP_SUPPORTED);
if (chip->docking_supported) {
fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
}
}
static void i82801gx_lpc_read_resources(device_t dev)