soc/intel/cannonlake: Add bootblock.c

Change-Id: Ia951a466479b1e98e49895705162a66aece7609b
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Andrey Petrov 2017-06-05 13:21:48 -07:00 committed by Martin Roth
parent 0405de9784
commit ab85e2b816
3 changed files with 153 additions and 0 deletions

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Intel Corporation..
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <intelblocks/gspi.h>
#include <soc/bootblock.h>
#include <soc/iomap.h>
#include <soc/pch.h>
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
/* Call lib/bootblock.c main */
bootblock_main_with_timestamp(base_timestamp);
}
void bootblock_soc_early_init(void)
{
bootblock_systemagent_early_init();
bootblock_pch_early_init();
bootblock_cpu_init();
pch_early_iorange_init();
if (IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM))
pch_uart_init();
}
void bootblock_soc_init(void)
{
report_platform_info();
set_max_freq();
pch_early_init();
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SOC_CANNONLAKE_BOOTBLOCK_H_
#define _SOC_CANNONLAKE_BOOTBLOCK_H_
#include <intelblocks/systemagent.h>
/* Bootblock pre console init programing */
void bootblock_cpu_init(void);
void bootblock_pch_early_init(void);
/* Bootblock post console init programing */
void pch_early_init(void);
void pch_early_iorange_init(void);
void report_platform_info(void);
void set_max_freq(void);
#endif

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SOC_CANNONLAKE_IOMAP_H_
#define _SOC_CANNONLAKE_IOMAP_H_
/*
* Memory-mapped I/O registers.
*/
#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
#define MCFG_BASE_SIZE 0x4000000
#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000
#define PCH_PRESERVED_BASE_SIZE 0x02000000
#define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000
#define PCH_TRACE_HUB_BASE_SIZE 0x00800000
#define UART_DEBUG_BASE_ADDRESS 0xfe036000
#define UART_DEBUG_BASE_SIZE 0x1000
#define EARLY_I2C_BASE_ADDRESS 0xfe040000
#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
#define MCH_BASE_ADDRESS 0xfed10000
#define MCH_BASE_SIZE 0x8000
#define DMI_BASE_ADDRESS 0xfeda0000
#define DMI_BASE_SIZE 0x1000
#define EP_BASE_ADDRESS 0xfeda1000
#define EP_BASE_SIZE 0x1000
#define EDRAM_BASE_ADDRESS 0xfed80000
#define EDRAM_BASE_SIZE 0x4000
#define REG_BASE_ADDRESS 0xfc000000
#define REG_BASE_SIZE 0x1000
#define HPET_BASE_ADDRESS 0xfed00000
#define PCH_PWRM_BASE_ADDRESS 0xfe000000
#define PCH_PWRM_BASE_SIZE 0x10000
#define SPI_BASE_ADDRESS 0xfe010000
#define EARLY_GSPI_BASE_ADDRESS 0xfe011000
#define GPIO_BASE_SIZE 0x10000
#define HECI1_BASE_ADDRESS 0xFEDA2000
/* CPU Trace reserved memory size */
#define TRACE_MEMORY_SIZE 0x8000000 /* 128MiB */
/*
* I/O port address space
*/
#define SMBUS_BASE_ADDRESS 0x0efa0
#define SMBUS_BASE_SIZE 0x20
#define ACPI_BASE_ADDRESS 0x1800
#define ACPI_BASE_SIZE 0x100
#define TCO_BASE_ADDRESS 0x400
#define TCO_BASE_SIZE 0x20
#endif