soc/intel/cannonlake: Add bootblock.c
Change-Id: Ia951a466479b1e98e49895705162a66aece7609b Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corporation..
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <intelblocks/gspi.h>
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#include <soc/bootblock.h>
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#include <soc/iomap.h>
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#include <soc/pch.h>
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asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
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{
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/* Call lib/bootblock.c main */
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bootblock_main_with_timestamp(base_timestamp);
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}
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void bootblock_soc_early_init(void)
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{
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bootblock_systemagent_early_init();
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bootblock_pch_early_init();
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bootblock_cpu_init();
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pch_early_iorange_init();
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if (IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM))
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pch_uart_init();
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}
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void bootblock_soc_init(void)
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{
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report_platform_info();
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set_max_freq();
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pch_early_init();
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_CANNONLAKE_BOOTBLOCK_H_
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#define _SOC_CANNONLAKE_BOOTBLOCK_H_
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#include <intelblocks/systemagent.h>
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/* Bootblock pre console init programing */
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void bootblock_cpu_init(void);
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void bootblock_pch_early_init(void);
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/* Bootblock post console init programing */
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void pch_early_init(void);
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void pch_early_iorange_init(void);
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void report_platform_info(void);
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void set_max_freq(void);
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#endif
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_CANNONLAKE_IOMAP_H_
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#define _SOC_CANNONLAKE_IOMAP_H_
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/*
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* Memory-mapped I/O registers.
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*/
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#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
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#define MCFG_BASE_SIZE 0x4000000
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#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000
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#define PCH_PRESERVED_BASE_SIZE 0x02000000
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#define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000
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#define PCH_TRACE_HUB_BASE_SIZE 0x00800000
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#define UART_DEBUG_BASE_ADDRESS 0xfe036000
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#define UART_DEBUG_BASE_SIZE 0x1000
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#define EARLY_I2C_BASE_ADDRESS 0xfe040000
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#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
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#define MCH_BASE_ADDRESS 0xfed10000
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#define MCH_BASE_SIZE 0x8000
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#define DMI_BASE_ADDRESS 0xfeda0000
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#define DMI_BASE_SIZE 0x1000
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#define EP_BASE_ADDRESS 0xfeda1000
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#define EP_BASE_SIZE 0x1000
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#define EDRAM_BASE_ADDRESS 0xfed80000
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#define EDRAM_BASE_SIZE 0x4000
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#define REG_BASE_ADDRESS 0xfc000000
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#define REG_BASE_SIZE 0x1000
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#define HPET_BASE_ADDRESS 0xfed00000
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#define PCH_PWRM_BASE_ADDRESS 0xfe000000
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#define PCH_PWRM_BASE_SIZE 0x10000
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#define SPI_BASE_ADDRESS 0xfe010000
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#define EARLY_GSPI_BASE_ADDRESS 0xfe011000
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#define GPIO_BASE_SIZE 0x10000
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#define HECI1_BASE_ADDRESS 0xFEDA2000
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/* CPU Trace reserved memory size */
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#define TRACE_MEMORY_SIZE 0x8000000 /* 128MiB */
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/*
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* I/O port address space
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*/
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#define SMBUS_BASE_ADDRESS 0x0efa0
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#define SMBUS_BASE_SIZE 0x20
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#define ACPI_BASE_ADDRESS 0x1800
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#define ACPI_BASE_SIZE 0x100
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#define TCO_BASE_ADDRESS 0x400
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#define TCO_BASE_SIZE 0x20
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#endif
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