google/reef: Write protect GPIO relative to bank offset

Update the write protect GPIO reported in ACPI to GPIO_75.
Also update the controller ID to "INT3452:01" which will
point at the goldmont device and includes write protect GPIO.

BUG=chrome-os-partner:55604
BRANCH=none
TEST=verify crossystem output for wpsw_cur.

Change-Id: Ibe6a013aaab18bfa2436698298177218ca934fab
Signed-off-by: Susendra Selvaraj <susendra.selvaraj@intel.com>
Reviewed-on: https://coreboot.intel.com/7929
Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com>
Tested-by: Petrov, Andrey <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15691
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Susendra Selvaraj 2016-06-22 03:52:03 +05:30 committed by Martin Roth
parent df12d1923f
commit ab88c7d366
1 changed files with 2 additions and 2 deletions

View File

@ -17,7 +17,7 @@
Name (OIPG, Package () {
/* No physical recovery GPIO. */
Package () { 0x0001, 0, 0xFFFFFFFF, "INT3452:00" },
Package () { 0x0001, 0, 0xFFFFFFFF, "INT3452:01" },
/* Firmware write protect GPIO. */
Package () { 0x0003, 1, GPIO_75, "INT3452:00" },
Package () { 0x0003, 1, PAD_NW(GPIO_75), "INT3452:01" },
})