Add extra phase before memory init.

Rename sdram_init to memory_init
NOTE: need to test sandpoint and ep boards!


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1603 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/arch/ppc/init/ppc_main.c

@@ -28,9 +28,20 @@ void ppc_main(void)
 	unsigned *from;
 	unsigned *to;
 
+	/*
+ 	 * very early board initialization
+	 */
 	board_init();
 
-	sdram_init();
+	/*
+	 * turn on memory
+	 */
+	memory_init();
+
+	/*
+	 * final initialization before jumping to payload
+	 */
+	board_init2();
 
 	/*
 	 * Flush cache now that memory is enabled.

src/cpu/ppc/ppc4xx/sdram.c

@@ -60,7 +60,7 @@
 
 /*-----------------------------------------------------------------------
  */
-void sdram_init(void)
+void memory_init(void)
 {
 #if 0
 	unsigned long speed;

src/mainboard/embeddedplanet/ep405pc/init.c

@@ -107,3 +107,8 @@ board_init(void)
 	udelay(100000);
 	out_8((unsigned char *)0xF4000009, 0x0E);
 }
+
+void
+board_init2(void)
+{
+}

src/mainboard/motorola/sandpoint/init.c

@@ -45,14 +45,11 @@ void pnp_output(char address, char data)
 void
 board_init(void)
 {
-	/*
+}
-	 * Configure FLASH
-	 */
 
-	/*
+void
-	 * Configure NVTRC/BCSR
+board_init2(void)
-	 */
+{
-	
 	/*
 	 * Enable UART0
 	 *
@@ -67,5 +64,5 @@ board_init(void)
 	pnp_output(0x61, TTYS0_BASE & 0xFF); /* IO Base */
 	pnp_output(0x30, 1); /* Activate */
 	uart8250_init(TTYS0_BASE, 115200/TTYS0_BAUD, TTYS0_LCS);
-	printk_info("Board initialized...\n");
+	printk_info("Sandpoint initialized...\n");
 }

src/mainboard/totalimpact/briq/init.c

@@ -31,11 +31,16 @@
 
 void
 board_init(void)
+{
+}
+
+void
+board_init2(void)
 {
         /*
          * Enable UART
          */
         uart8250_init(TTYS0_BASE, TTYS0_DIV, TTYS0_LCS);
-        printk_info("briQ board initialized...\n");
+        printk_info("briQ initialized...\n");
 
 }

src/northbridge/ibm/cpc710/cpc710.c

@@ -10,6 +10,7 @@
 	CPC710_MCCR_FIXED_BITS
 
 void cpc710_init(void);
+void sdram_init(void);
 extern void cpc710_pci_init(void);
 
 void
@@ -25,17 +26,16 @@ getCPC710(uint32_t addr)
 }
 
 void
-sdram_init(void)
+memory_init(void)
 {
 	cpc710_init();
+	sdram_init();
 	cpc710_pci_init();
 }
 
 void
 cpc710_init(void)
 {
-	uint32_t mccr;
-
 	setCPC710(CPC710_CPC0_RSTR,   0xf0000000);	
 	(void)getCPC710(CPC710_CPC0_MPSR);	
 	setCPC710(CPC710_CPC0_SIOC0,   0x00000000);	
@@ -55,6 +55,12 @@ cpc710_init(void)
 	setCPC710(CPC710_SDRAM0_MEAR,   0x00000000);	
 	setCPC710(CPC710_SDRAM0_MWPR,   0x00000000);	
 	setCPC710(CPC710_CPC0_RGBAN1, 0x00000000);	
+}
+
+void
+sdram_init()
+{
+	uint32_t mccr;
 
 	/*
 	 * Reset memory configuration

src/northbridge/motorola/mpc107/mpc107.c

@@ -35,7 +35,7 @@
 void mpc107_init(void);
 
 void 
-sdram_init(void)
+memory_init(void)
 {
 	struct sdram_dimm_info dimms[NUM_DIMMS];
 	struct sdram_bank_info banks[NUM_BANKS];