mainboard/{google,intel}: Remove SaGv hard coding

Remove hard coding for SaGv config in devicetree.cb and apply macro for
SaGv config for CNL variants boards

Change-Id: If007589d5c1368602928b1550ec8788e65f70c05
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Ronak Kanabar 2019-01-28 13:32:31 +05:30 committed by Patrick Georgi
parent 168f046d71
commit ab92f26a13
8 changed files with 8 additions and 8 deletions

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@ -14,7 +14,7 @@ chip soc/intel/cannonlake
register "gen3_dec" = "0x000c0951" # 0x950-0x95f
# FSP configuration
register "SaGv" = "3"
register "SaGv" = "SaGv_Enabled"
register "HeciEnabled" = "1"
register "SataSalpSupport" = "1"
register "SataMode" = "Sata_AHCI"

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@ -14,7 +14,7 @@ chip soc/intel/cannonlake
register "gen3_dec" = "0x000c0951" # 0x950-0x95f
# FSP configuration
register "SaGv" = "3"
register "SaGv" = "SaGv_Enabled"
register "HeciEnabled" = "1"
register "SataSalpSupport" = "1"
register "SataMode" = "Sata_AHCI"

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@ -5,7 +5,7 @@ chip soc/intel/cannonlake
end
# FSP configuration
register "SaGv" = "3"
register "SaGv" = "SaGv_FixedHigh"
register "ScsEmmcHs400Enabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"

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@ -5,7 +5,7 @@ chip soc/intel/cannonlake
end
# FSP configuration
register "SaGv" = "3"
register "SaGv" = "SaGv_FixedHigh"
register "ScsEmmcHs400Enabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"

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@ -5,7 +5,7 @@ chip soc/intel/cannonlake
end
# FSP configuration
register "SaGv" = "3"
register "SaGv" = "SaGv_Enabled"
register "RMT" = "1"
register "ScsEmmcHs400Enabled" = "1"

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@ -5,7 +5,7 @@ chip soc/intel/cannonlake
end
# FSP configuration
register "SaGv" = "3"
register "SaGv" = "SaGv_Enabled"
register "RMT" = "1"
register "ScsEmmcHs400Enabled" = "1"

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@ -5,7 +5,7 @@ chip soc/intel/cannonlake
end
# FSP configuration
register "SaGv" = "3"
register "SaGv" = "SaGv_Enabled"
register "ScsEmmcHs400Enabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"

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@ -5,7 +5,7 @@ chip soc/intel/cannonlake
end
# FSP configuration
register "SaGv" = "3"
register "SaGv" = "SaGv_Enabled"
register "ScsEmmcHs400Enabled" = "1"
register "HeciEnabled" = "1"