intel/common/block/itss: Extend itss_irq_init() to handle IOSF 1.0
Current implementation of itss_irq_init() uses 8 bit write access to IRQ routing registers which is not supported on Apollo Lake. This commit moves the register access from 8 bit to 32 bit so that this function can be used with every platform. Change-Id: I15c3c33a16329fd57f0ad7f99d720adbf300d094 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/20680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
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* This file is part of the coreboot project.
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*
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*
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* Copyright (C) 2017 Intel Corporation.
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* Copyright (C) 2017 Intel Corporation.
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* Copyright (C) 2017 Siemens AG
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* it under the terms of the GNU General Public License as published by
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@ -23,18 +24,27 @@
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void itss_irq_init(uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG])
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void itss_irq_init(uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG])
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{
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{
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uint8_t index = 0;
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uint32_t regs[MAX_PXRC_CONFIG/sizeof(uint32_t)] = {0};
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uint8_t index, byte;
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for (index = 0; index < MAX_PXRC_CONFIG; index++) {
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/* Fill in all the PIRx routes into one array. */
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uint8_t val = pch_interrupt_routing[index];
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for (index = 0; index < ARRAY_SIZE(regs); index++) {
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uint8_t irq = val & 0xf;
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for (byte = 0; byte < sizeof(uint32_t); byte++) {
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uint8_t val = pch_interrupt_routing[index *
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sizeof(uint32_t) + byte];
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uint8_t irq = val & 0xf;
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if (irq == 8 || irq == 13)
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if ((irq <= 2) || (irq == 8) || (irq == 13))
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continue;
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regs[index] |= (0x80 << (8 * byte));
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if (irq <= 2)
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else
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continue;
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regs[index] |= (val << (8 * byte));
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}
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pcr_write8(PID_ITSS, PCR_ITSS_PIRQA_ROUT + index, val);
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/* Access the routing register in 32 bit mode to make this
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function suitable for both IOSF 1.0 (where only 32 bit access
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is supported) and later versions of the interface. */
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pcr_write32(PID_ITSS,
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PCR_ITSS_PIRQA_ROUT + (index * sizeof(uint32_t)),
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regs[index]);
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}
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}
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}
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}
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