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intel/i945,gm45,pineview,x4x: Move stage cache support function 

Let garbage-collection take care of stage_cache_external_region()
when it is not needed and move implementation to a suitable file
already building for needed stages.

Change-Id: Ic32adcc62c7ee21bf38e2e4e5ece00524871b091
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki 2019-08-02 06:11:28 +03:00 committed by Martin Roth
parent 26a682c944
commit aba8fb1158
12 changed files with 50 additions and 130 deletions
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4
src/northbridge/intel/gm45/Makefile.inc
View File

@ -39,8 +39,4 @@ smm-y += ../../../cpu/x86/lapic/apic_timer.c
postcar-y += ram_calc.c
romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
endif

12
src/northbridge/intel/gm45/ram_calc.c
View File

@ -26,6 +26,7 @@
#include <cpu/x86/mtrr.h>
#include <cbmem.h>
#include <program_loading.h>
#include <stage_cache.h>
#include <cpu/intel/smm/gen1/smi.h>
#include "gm45.h"
@ -123,6 +124,17 @@ void *cbmem_top(void)
return (void *) top_of_ram;
}
void stage_cache_external_region(void **base, size_t *size)
{
/*
* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
* The top of RAM is defined to be the TSEG base address.
*/
*size = CONFIG_SMM_RESERVED_SIZE;
*base = (void *)(northbridge_get_tseg_base()
+ CONFIG_SMM_RESERVED_SIZE);
}
/* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use,
* and continues execution in postcar stage. */

29
src/northbridge/intel/gm45/stage_cache.c
View File

@ -1,29 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <stage_cache.h>
#include <cpu/intel/smm/gen1/smi.h>
void stage_cache_external_region(void **base, size_t *size)
{
/*
* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
* The top of RAM is defined to be the TSEG base address.
*/
*size = CONFIG_SMM_RESERVED_SIZE;
*base = (void *)(northbridge_get_tseg_base()
+ CONFIG_SMM_RESERVED_SIZE);
}

4
src/northbridge/intel/i945/Makefile.inc
View File

@ -31,8 +31,4 @@ smm-y += udelay.c
postcar-y += ram_calc.c
romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
endif

13
src/northbridge/intel/i945/ram_calc.c
View File

@ -25,6 +25,8 @@
#include <cpu/x86/mtrr.h>
#include <program_loading.h>
#include <cpu/intel/smm/gen1/smi.h>
#include <stdint.h>
#include <stage_cache.h>
/* Decodes TSEG region size to bytes. */
u32 decode_tseg_size(const u8 esmramc)
@ -88,6 +90,17 @@ u32 decode_igd_memory_size(const u32 gms)
return ggc2uma[gms] << 10;
}
void stage_cache_external_region(void **base, size_t *size)
{
/*
* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
* The top of RAM is defined to be the TSEG base address.
*/
*size = CONFIG_SMM_RESERVED_SIZE;
*base = (void *)(northbridge_get_tseg_base()
+ CONFIG_SMM_RESERVED_SIZE);
}
/* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use,
* and continues execution in postcar stage. */

29
src/northbridge/intel/i945/stage_cache.c
View File

@ -1,29 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <stage_cache.h>
#include <cpu/intel/smm/gen1/smi.h>
void stage_cache_external_region(void **base, size_t *size)
{
/*
* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
* The top of RAM is defined to be the TSEG base address.
*/
*size = CONFIG_SMM_RESERVED_SIZE;
*base = (void *)(northbridge_get_tseg_base()
+ CONFIG_SMM_RESERVED_SIZE);
}

3
src/northbridge/intel/pineview/Makefile.inc
View File

@ -30,8 +30,5 @@ romstage-y += raminit.c
romstage-y += early_init.c
postcar-y += ram_calc.c
romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
endif

13
src/northbridge/intel/pineview/ram_calc.c
View File

@ -26,6 +26,8 @@
#include <cpu/x86/mtrr.h>
#include <cpu/intel/romstage.h>
#include <cpu/intel/smm/gen1/smi.h>
#include <stdint.h>
#include <stage_cache.h>
u8 decode_pciebar(u32 *const base, u32 *const len)
{
@ -138,6 +140,17 @@ void *cbmem_top(void)
}
void stage_cache_external_region(void **base, size_t *size)
{
/*
* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
* The top of RAM is defined to be the TSEG base address.
*/
*size = CONFIG_SMM_RESERVED_SIZE;
*base = (void *)(northbridge_get_tseg_base()
+ CONFIG_SMM_RESERVED_SIZE);
}
/* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use,
* and continues execution in postcar stage. */

29
src/northbridge/intel/pineview/stage_cache.c
View File

@ -1,29 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <stage_cache.h>
#include <cpu/intel/smm/gen1/smi.h>
void stage_cache_external_region(void **base, size_t *size)
{
/*
* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
* The top of RAM is defined to be the TSEG base address.
*/
*size = CONFIG_SMM_RESERVED_SIZE;
*base = (void *)(northbridge_get_tseg_base()
+ CONFIG_SMM_RESERVED_SIZE);
}

3
src/northbridge/intel/x4x/Makefile.inc
View File

@ -30,8 +30,5 @@ ramstage-y += gma.c
ramstage-y += northbridge.c
postcar-y += ram_calc.c
romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
endif

12
src/northbridge/intel/x4x/ram_calc.c
View File

@ -29,6 +29,7 @@
#include <northbridge/intel/x4x/x4x.h>
#include <program_loading.h>
#include <cpu/intel/smm/gen1/smi.h>
#include <stage_cache.h>
/** Decodes used Graphics Mode Select (GMS) to kilobytes. */
u32 decode_igd_memory_size(const u32 gms)
@ -134,6 +135,17 @@ void *cbmem_top(void)
return (void *) top_of_ram;
}
void stage_cache_external_region(void **base, size_t *size)
{
/*
* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
* The top of RAM is defined to be the TSEG base address.
*/
*size = CONFIG_SMM_RESERVED_SIZE;
*base = (void *)(northbridge_get_tseg_base()
+ CONFIG_SMM_RESERVED_SIZE);
}
/* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use,
* and continues execution in postcar stage. */

29
src/northbridge/intel/x4x/stage_cache.c
View File

@ -1,29 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <stage_cache.h>
#include <cpu/intel/smm/gen1/smi.h>
void stage_cache_external_region(void **base, size_t *size)
{
/*
* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
* The top of RAM is defined to be the TSEG base address.
*/
*size = CONFIG_SMM_RESERVED_SIZE;
*base = (void *)(northbridge_get_tseg_base()
+ CONFIG_SMM_RESERVED_SIZE);
}