baytrail: Clean up NVS region
There is a lot of NVS allocated to things that are not really used. Most of these are removed and some are moved around. Thermals are expected to be handled with DPTF so I've removed that bit of code but have not yet cleaned up the thermal zone. I left in the SIO BARs since I think we will need those still even though they may need work still. BUG=chrome-os-partner:23505 BRANCH=rambi TEST=build and boot on rambi Change-Id: Id16ee67e6b3709a303c001afd72947147f938127 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175626 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4936 Tested-by: build bot (Jenkins)
This commit is contained in:
Duncan Laurie
Aaron Durbin
parent
1f52f51f4e
commit
abab05cb3c
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@ -30,45 +30,16 @@
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#include <device/pci_ids.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/msr.h>
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#include <ec/google/chromeec/ec.h>
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#include <vendorcode/google/chromeos/gnvs.h>
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#include <baytrail/acpi.h>
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#include <baytrail/nvs.h>
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#include <baytrail/iomap.h>
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extern const unsigned char AmlCode[];
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#include "thermal.h"
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static void acpi_update_thermal_table(global_nvs_t *gnvs)
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{
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gnvs->f4of = FAN4_THRESHOLD_OFF;
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gnvs->f4on = FAN4_THRESHOLD_ON;
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gnvs->f4pw = FAN4_PWM;
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gnvs->f3of = FAN3_THRESHOLD_OFF;
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gnvs->f3on = FAN3_THRESHOLD_ON;
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gnvs->f3pw = FAN3_PWM;
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gnvs->f2of = FAN2_THRESHOLD_OFF;
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gnvs->f2on = FAN2_THRESHOLD_ON;
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gnvs->f2pw = FAN2_PWM;
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gnvs->f1of = FAN1_THRESHOLD_OFF;
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gnvs->f1on = FAN1_THRESHOLD_ON;
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gnvs->f1pw = FAN1_PWM;
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gnvs->f0of = FAN0_THRESHOLD_OFF;
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gnvs->f0on = FAN0_THRESHOLD_ON;
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gnvs->f0pw = FAN0_PWM;
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gnvs->tcrt = CRITICAL_TEMPERATURE;
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gnvs->tpsv = PASSIVE_TEMPERATURE;
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gnvs->tmax = MAX_TEMPERATURE;
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}
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static void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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gnvs->apic = 1;
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gnvs->mpen = 1; /* Enable Multi Processing */
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gnvs->pcnt = dev_count_cpu();
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/* Enable USB ports in S3 */
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@ -82,28 +53,20 @@ static void acpi_create_gnvs(global_nvs_t *gnvs)
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/* CBMEM TOC */
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gnvs->cmem = 0;
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/* Top of Low Memory (start of resource allocation) */
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gnvs->tolm = nc_read_top_of_low_memory();
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/* TPM Present */
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gnvs->tpmp = 1;
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/* IGD Displays */
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gnvs->ndid = 3;
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gnvs->did[0] = 0x80000100;
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gnvs->did[1] = 0x80000240;
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gnvs->did[2] = 0x80000410;
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gnvs->did[3] = 0x80000410;
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gnvs->did[4] = 0x00000005;
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#if CONFIG_CHROMEOS
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// TODO(reinauer) this could move elsewhere?
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chromeos_init_vboot(&(gnvs->chromeos));
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/* Emerald Lake has no EC (?) */
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gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
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gnvs->chromeos.vbt2 = google_ec_running_ro() ?
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ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
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#endif
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/* Update the mem console pointer. */
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gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
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acpi_update_thermal_table(gnvs);
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}
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unsigned long acpi_fill_madt(unsigned long current)
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@ -22,7 +22,6 @@
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/* Global Variables */
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Name(\PICM, 0) // IOAPIC/8259
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Name(\DSEN, 1) // Display Output Switching Enable
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/* Global ACPI memory region. This region is used for passing information
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* between coreboot (aka "the system bios"), ACPI, and the SMI handler.
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@ -49,69 +48,23 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
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P80D, 32, // 0x0b - Debug port (IO 0x80) value
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LIDS, 8, // 0x0f - LID state (open = 1)
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PWRS, 8, // 0x10 - Power State (AC = 1)
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/* Thermal policy */
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Offset (0x11),
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TLVL, 8, // 0x11 - Throttle Level Limit
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FLVL, 8, // 0x12 - Current FAN Level
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TCRT, 8, // 0x13 - Critical Threshold
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TPSV, 8, // 0x14 - Passive Threshold
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TMAX, 8, // 0x15 - CPU Tj_max
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F0OF, 8, // 0x16 - FAN 0 OFF Threshold
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F0ON, 8, // 0x17 - FAN 0 ON Threshold
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F0PW, 8, // 0x18 - FAN 0 PWM value
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F1OF, 8, // 0x19 - FAN 1 OFF Threshold
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F1ON, 8, // 0x1a - FAN 1 ON Threshold
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F1PW, 8, // 0x1b - FAN 1 PWM value
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F2OF, 8, // 0x1c - FAN 2 OFF Threshold
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F2ON, 8, // 0x1d - FAN 2 ON Threshold
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F2PW, 8, // 0x1e - FAN 2 PWM value
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F3OF, 8, // 0x1f - FAN 3 OFF Threshold
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F3ON, 8, // 0x20 - FAN 3 ON Threshold
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F3PW, 8, // 0x21 - FAN 3 PWM value
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F4OF, 8, // 0x22 - FAN 4 OFF Threshold
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F4ON, 8, // 0x23 - FAN 4 ON Threshold
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F4PW, 8, // 0x24 - FAN 4 PWM value
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TMPS, 8, // 0x25 - Temperature Sensor ID
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/* Processor Identification */
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Offset (0x28),
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APIC, 8, // 0x28 - APIC Enabled by coreboot
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MPEN, 8, // 0x29 - Multi Processor Enable
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PCP0, 8, // 0x2a - PDC CPU/CORE 0
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PCP1, 8, // 0x2b - PDC CPU/CORE 1
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PPCM, 8, // 0x2c - Max. PPC state
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PCNT, 8, // 0x2d - Processor count
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/* Super I/O & CMOS config */
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Offset (0x32),
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NATP, 8, // 0x32 -
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S5U0, 8, // 0x33 - Enable USB0 in S5
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S5U1, 8, // 0x34 - Enable USB1 in S5
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S3U0, 8, // 0x35 - Enable USB0 in S3
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S3U1, 8, // 0x36 - Enable USB1 in S3
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S33G, 8, // 0x37 - Enable 3G in S3
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CMEM, 32, // 0x38 - CBMEM TOC
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/* Integrated Graphics Device */
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Offset (0x3c),
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IGDS, 8, // 0x3c - IGD state (primary = 1)
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TLST, 8, // 0x3d - Display Toggle List pointer
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CADL, 8, // 0x3e - Currently Attached Devices List
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PADL, 8, // 0x3f - Previously Attached Devices List
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CSTE, 16, // 0x40 - Current display state
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NSTE, 16, // 0x42 - Next display state
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SSTE, 16, // 0x44 - Set display state
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Offset (0x46),
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NDID, 8, // 0x46 - Number of Device IDs
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DID1, 32, // 0x47 - Device ID 1
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DID2, 32, // 0x4b - Device ID 2
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DID3, 32, // 0x4f - Device ID 3
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DID4, 32, // 0x53 - Device ID 4
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DID5, 32, // 0x57 - Device ID 5
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PCNT, 8, // 0x11 - Processor count
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TPMP, 8, // 0x12 - TPM Present and Enabled
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/* TPM support */
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Offset (0x5b),
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TPMP, 8, // 0x5b - TPM Present
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TPME, 8, // 0x5c - TPM Enable
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/* Device Config */
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Offset (0x20),
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S5U0, 8, // 0x20 - Enable USB0 in S5
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S5U1, 8, // 0x21 - Enable USB1 in S5
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S3U0, 8, // 0x22 - Enable USB0 in S3
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S3U1, 8, // 0x23 - Enable USB1 in S3
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/* LynxPoint Serial IO device BARs */
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/* Base addresses */
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Offset (0x30),
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CMEM, 32, // 0x30 - CBMEM TOC
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TOLM, 32, // 0x34 - Top of Low Memory
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CBMC, 32, // 0x38 - coreboot mem console pointer
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/* Serial IO device BARs */
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Offset (0x60),
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S0B0, 32, // 0x60 - D21:F0 Serial IO SDMA BAR0
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S1B0, 32, // 0x64 - D21:F1 Serial IO I2C0 BAR0
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@ -130,51 +83,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
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S6B1, 32, // 0x98 - D21:F6 Serial IO UAR1 BAR1
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S7B1, 32, // 0x9c - D23:F0 Serial IO SDIO BAR1
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Offset (0xa0),
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CBMC, 32, // 0xa0 - coreboot mem console pointer
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/* IGD OpRegion */
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Offset (0xb4),
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ASLB, 32, // 0xb4 - IGD OpRegion Base Address
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IBTT, 8, // 0xb8 - IGD boot panel device
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IPAT, 8, // 0xb9 - IGD panel type cmos option
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ITVF, 8, // 0xba - IGD TV format cmos option
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ITVM, 8, // 0xbb - IGD TV minor format option
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IPSC, 8, // 0xbc - IGD panel scaling
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IBLC, 8, // 0xbd - IGD BLC config
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IBIA, 8, // 0xbe - IGD BIA config
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ISSC, 8, // 0xbf - IGD SSC config
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I409, 8, // 0xc0 - IGD 0409 modified settings
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I509, 8, // 0xc1 - IGD 0509 modified settings
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I609, 8, // 0xc2 - IGD 0609 modified settings
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I709, 8, // 0xc3 - IGD 0709 modified settings
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IDMM, 8, // 0xc4 - IGD Power conservation feature
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IDMS, 8, // 0xc5 - IGD DVMT memory size
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IF1E, 8, // 0xc6 - IGD function 1 enable
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HVCO, 8, // 0xc7 - IGD HPLL VCO
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NXD1, 32, // 0xc8 - IGD _DGS next DID1
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NXD2, 32, // 0xcc - IGD _DGS next DID2
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NXD3, 32, // 0xd0 - IGD _DGS next DID3
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NXD4, 32, // 0xd4 - IGD _DGS next DID4
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NXD5, 32, // 0xd8 - IGD _DGS next DID5
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NXD6, 32, // 0xdc - IGD _DGS next DID6
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NXD7, 32, // 0xe0 - IGD _DGS next DID7
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NXD8, 32, // 0xe4 - IGD _DGS next DID8
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ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI)
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PAVP, 8, // 0xe9 - IGD PAVP data
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Offset (0xeb),
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OSCC, 8, // 0xeb - PCIe OSC control
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NPCE, 8, // 0xec - native pcie support
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PLFL, 8, // 0xed - platform flavor
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BREV, 8, // 0xee - board revision
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DPBM, 8, // 0xef - digital port b mode
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DPCM, 8, // 0xf0 - digital port c mode
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DPDM, 8, // 0xf1 - digital port d mode
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ALFP, 8, // 0xf2 - active lfp
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IMON, 8, // 0xf3 - current graphics turbo imon value
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MMIO, 8, // 0xf4 - 64bit mmio support
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/* ChromeOS specific */
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Offset (0x100),
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#include <vendorcode/google/chromeos/acpi/gnvs.asl>
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@ -207,78 +115,3 @@ Method (S5UD)
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Store (Zero, \S5U0)
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Store (Zero, \S5U1)
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}
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/* Set flag to enable 3G module in S3 */
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Method (S3GE)
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{
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Store (One, \S33G)
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}
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/* Set flag to disable 3G module in S3 */
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Method (S3GD)
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{
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Store (Zero, \S33G)
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}
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External (\_TZ.THRM)
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External (\_TZ.SKIN)
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Method (TZUP)
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{
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/* Update Primary Thermal Zone */
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If (CondRefOf (\_TZ.THRM, Local0)) {
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Notify (\_TZ.THRM, 0x81)
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}
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/* Update Secondary Thermal Zone */
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If (CondRefOf (\_TZ.SKIN, Local0)) {
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Notify (\_TZ.SKIN, 0x81)
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}
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}
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/* Update Fan 0 thresholds */
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Method (F0UT, 2)
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{
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Store (Arg0, \F0OF)
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Store (Arg1, \F0ON)
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TZUP ()
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}
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/* Update Fan 1 thresholds */
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Method (F1UT, 2)
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{
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Store (Arg0, \F1OF)
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Store (Arg1, \F1ON)
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TZUP ()
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}
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/* Update Fan 2 thresholds */
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Method (F2UT, 2)
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{
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Store (Arg0, \F2OF)
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Store (Arg1, \F2ON)
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TZUP ()
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}
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/* Update Fan 3 thresholds */
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Method (F3UT, 2)
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{
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Store (Arg0, \F3OF)
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Store (Arg1, \F3ON)
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TZUP ()
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}
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/* Update Fan 4 thresholds */
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Method (F4UT, 2)
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{
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Store (Arg0, \F4OF)
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Store (Arg1, \F4ON)
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TZUP ()
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}
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/* Update Temperature Sensor ID */
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Method (TMPU, 1)
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{
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Store (Arg0, \TMPS)
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TZUP ()
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}
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@ -34,97 +34,27 @@ typedef struct {
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u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
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u8 lids; /* 0x0f - LID state (open = 1) */
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u8 pwrs; /* 0x10 - Power state (AC = 1) */
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/* Thermal policy */
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u8 tlvl; /* 0x11 - Throttle Level Limit */
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u8 flvl; /* 0x12 - Current FAN Level */
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u8 tcrt; /* 0x13 - Critical Threshold */
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u8 tpsv; /* 0x14 - Passive Threshold */
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u8 tmax; /* 0x15 - CPU Tj_max */
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u8 f0of; /* 0x16 - FAN 0 OFF Threshold */
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u8 f0on; /* 0x17 - FAN 0 ON Threshold */
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u8 f0pw; /* 0x18 - FAN 0 PWM value */
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u8 f1of; /* 0x19 - FAN 1 OFF Threshold */
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u8 f1on; /* 0x1a - FAN 1 ON Threshold */
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u8 f1pw; /* 0x1b - FAN 1 PWM value */
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u8 f2of; /* 0x1c - FAN 2 OFF Threshold */
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u8 f2on; /* 0x1d - FAN 2 ON Threshold */
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u8 f2pw; /* 0x1e - FAN 2 PWM value */
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u8 f3of; /* 0x1f - FAN 3 OFF Threshold */
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u8 f3on; /* 0x20 - FAN 3 ON Threshold */
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u8 f3pw; /* 0x21 - FAN 3 PWM value */
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u8 f4of; /* 0x22 - FAN 4 OFF Threshold */
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u8 f4on; /* 0x23 - FAN 4 ON Threshold */
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u8 f4pw; /* 0x24 - FAN 4 PWM value */
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u8 tmps; /* 0x25 - Temperature Sensor ID */
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u8 rsvd3[2];
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/* Processor Identification */
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u8 apic; /* 0x28 - APIC enabled */
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u8 mpen; /* 0x29 - MP capable/enabled */
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u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
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u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
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u8 ppcm; /* 0x2c - Max. PPC state */
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u8 pcnt; /* 0x2d - Processor Count */
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u8 rsvd4[4];
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/* Super I/O & CMOS config */
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u8 natp; /* 0x32 - SIO type */
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u8 s5u0; /* 0x33 - Enable USB0 in S5 */
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u8 s5u1; /* 0x34 - Enable USB1 in S5 */
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u8 s3u0; /* 0x35 - Enable USB0 in S3 */
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u8 s3u1; /* 0x36 - Enable USB1 in S3 */
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u8 s33g; /* 0x37 - Enable S3 in 3G */
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u32 cmem; /* 0x38 - CBMEM TOC */
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/* Integrated Graphics Device */
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u8 igds; /* 0x3c - IGD state */
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u8 tlst; /* 0x3d - Display Toggle List Pointer */
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u8 cadl; /* 0x3e - currently attached devices */
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u8 padl; /* 0x3f - previously attached devices */
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u16 cste; /* 0x40 - current display state */
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u16 nste; /* 0x42 - next display state */
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u16 sste; /* 0x44 - set display state */
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u8 ndid; /* 0x46 - number of device ids */
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u32 did[5]; /* 0x47 - 5b device id 1..5 */
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/* TPM support */
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u8 tpmp; /* 0x5b - TPM Present */
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u8 tpme; /* 0x5c - TPM Enable */
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u8 rsvd5[3];
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/* LynxPoint Serial IO device BARs */
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u8 pcnt; /* 0x11 - Processor Count */
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u8 tpmp; /* 0x12 - TPM Present and Enabled */
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u8 rsvd1[13];
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/* Device Config */
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u8 s5u0; /* 0x20 - Enable USB0 in S5 */
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u8 s5u1; /* 0x21 - Enable USB1 in S5 */
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u8 s3u0; /* 0x22 - Enable USB0 in S3 */
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u8 s3u1; /* 0x23 - Enable USB1 in S3 */
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u8 rsvd2[12];
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/* Base Addresses */
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u32 cmem; /* 0x30 - CBMEM TOC */
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u32 tolm; /* 0x34 - Top of Low Memory */
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u32 cbmc; /* 0x38 - coreboot memconsole */
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u8 rsvd5[39];
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/* Serial IO device BARs */
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u32 s0b[8]; /* 0x60 - 0x7f - BAR0 */
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u32 s1b[8]; /* 0x80 - 0x9f - BAR1 */
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u32 cbmc; /* 0xa0 - 0xa3 - coreboot memconsole */
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u8 rsvd6[16];
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/* IGD OpRegion (not implemented yet) */
|
||||
u32 aslb; /* 0xb4 - IGD OpRegion Base Address */
|
||||
u8 ibtt; /* 0xb8 - IGD boot type */
|
||||
u8 ipat; /* 0xb9 - IGD panel type */
|
||||
u8 itvf; /* 0xba - IGD TV format */
|
||||
u8 itvm; /* 0xbb - IGD TV minor format */
|
||||
u8 ipsc; /* 0xbc - IGD Panel Scaling */
|
||||
u8 iblc; /* 0xbd - IGD BLC configuration */
|
||||
u8 ibia; /* 0xbe - IGD BIA configuration */
|
||||
u8 issc; /* 0xbf - IGD SSC configuration */
|
||||
u8 i409; /* 0xc0 - IGD 0409 modified settings */
|
||||
u8 i509; /* 0xc1 - IGD 0509 modified settings */
|
||||
u8 i609; /* 0xc2 - IGD 0609 modified settings */
|
||||
u8 i709; /* 0xc3 - IGD 0709 modified settings */
|
||||
u8 idmm; /* 0xc4 - IGD Power Conservation */
|
||||
u8 idms; /* 0xc5 - IGD DVMT memory size */
|
||||
u8 if1e; /* 0xc6 - IGD Function 1 Enable */
|
||||
u8 hvco; /* 0xc7 - IGD HPLL VCO */
|
||||
u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */
|
||||
u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */
|
||||
u8 pavp; /* 0xe9 - IGD PAVP data */
|
||||
u8 rsvd12; /* 0xea - rsvd */
|
||||
u8 oscc; /* 0xeb - PCIe OSC control */
|
||||
u8 npce; /* 0xec - native pcie support */
|
||||
u8 plfl; /* 0xed - platform flavor */
|
||||
u8 brev; /* 0xee - board revision */
|
||||
u8 dpbm; /* 0xef - digital port b mode */
|
||||
u8 dpcm; /* 0xf0 - digital port c mode */
|
||||
u8 dpdm; /* 0xf1 - digital port c mode */
|
||||
u8 alfp; /* 0xf2 - active lfp */
|
||||
u8 imon; /* 0xf3 - current graphics turbo imon value */
|
||||
u8 mmio; /* 0xf4 - 64bit mmio support */
|
||||
u8 rsvd13[11]; /* 0xf5 - rsvd */
|
||||
u8 rsvd6[95];
|
||||
|
||||
/* ChromeOS specific (starts at 0x100)*/
|
||||
chromeos_acpi_t chromeos;
|
||||
|
|
|
|||
Loading…
Reference in New Issue