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mb/google/brya: Lock TPM IRQ pin in brask and brya baseboards 

This applies a configuration lock to the TPM IRQ pins for all brya
and brask variants.

BUG=b:208827718
TEST=cat /sys/kernel/debug/pinctrl/INTC1055\:00/pins suggests
GSC_PCH_INT_ODL is locked.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Icfc251152278c59f9a94b84fcd8c6d36c26bff62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This commit is contained in:
Subrata Banik 2022-01-31 23:15:25 +05:30
parent da2827779c
commit abac030662
2 changed files with 2 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/brya/variants/baseboard/brask/gpio.c
View File

@ -29,7 +29,7 @@ static const struct pad_config gpio_table[] = {
/* A12 : SATAXPCIE1 ==> CLKREQ_9B */
PAD_NC(GPP_A12, NONE),
/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG),
/* A14 : USB_OC1# ==> USB_C1_OC_ODL */
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
/* A15 : USB_OC2# ==> USB_C2_OC_ODL */

3
src/mainboard/google/brya/variants/baseboard/brya/gpio.c
View File

@ -29,7 +29,7 @@ static const struct pad_config gpio_table[] = {
/* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */
PAD_CFG_GPO(GPP_A12, 1, DEEP),
/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG),
/* A14 : USB_OC1# ==> USB_C1_OC_ODL */
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
/* A15 : USB_OC2# ==> USB_C2_OC_ODL */
@ -458,7 +458,6 @@ const struct pad_config *__weak variant_romstage_gpio_table(size_t *num)
}
static struct gpio_lock_config lockable_brya_gpios[] = {
{ GPP_A13, GPIO_LOCK_CONFIG }, /* GSC_PCH_INT_ODL */
{ GPP_E15, GPIO_LOCK_CONFIG }, /* PCH_WP_OD */
{ GPP_F11, GPIO_LOCK_CONFIG }, /* GSPI_PCH_CLK_FPMCU_R */
{ GPP_F13, GPIO_LOCK_CONFIG }, /* GSPI_PCH_D1_FPMCU_D0 */