GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/guybrush: Use register and bit defines for eSPI setup 

It's hard to understand what this code is doing because it uses hard
coded values, so use the register and bit defines instead.

BUG=none
TEST=Timeless build for guybrush results in identical binary.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2d74ed3b9b4984ab1e2a22c50375baf9c9589df0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Raul E Rangel 2021-08-19 11:43:29 -06:00 committed by Felix Held
parent 3df6f41928
commit abbb5b58ec
2 changed files with 23 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
src/mainboard/google/guybrush/bootblock.c
View File

@ -2,12 +2,15 @@
#include <amdblocks/acpimmio.h> #include <amdblocks/acpimmio.h>
#include <amdblocks/espi.h> #include <amdblocks/espi.h>
#include <amdblocks/lpc.h>
#include <bootblock_common.h> #include <bootblock_common.h>
#include <baseboard/variants.h> #include <baseboard/variants.h>
#include <console/console.h> #include <console/console.h>
#include <delay.h> #include <delay.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <soc/lpc.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <soc/southbridge.h>
#include <timer.h> #include <timer.h>
#define FC350_PCIE_INIT_DELAY_US (20 * USECS_PER_MSEC) #define FC350_PCIE_INIT_DELAY_US (20 * USECS_PER_MSEC)
@ -31,12 +34,13 @@ void bootblock_mainboard_early_init(void)
size_t base_num_gpios, override_num_gpios; size_t base_num_gpios, override_num_gpios;
const struct soc_amd_gpio *base_gpios, *override_gpios; const struct soc_amd_gpio *base_gpios, *override_gpios;
dword = pci_read_config32(SOC_LPC_DEV, 0x78); dword = pci_read_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS);
dword &= 0xFFFFF9F3; dword &= ~(LPC_LDRQ0_PU_EN | LPC_LDRQ0_PD_EN | LPC_LDRQ1_EN | LPC_LDRQ0_EN);
dword |= 0x200; dword |= LPC_LDRQ0_PD_EN;
pci_write_config32(SOC_LPC_DEV, 0x78, dword); pci_write_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS, dword);
pci_write_config32(SOC_LPC_DEV, 0x44, 0);
pci_write_config32(SOC_LPC_DEV, 0x48, 0); pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, 0);
pci_write_config32(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, 0);
if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK))
return; return;
@ -53,13 +57,13 @@ void bootblock_mainboard_early_init(void)
stopwatch_init_usecs_expire(&pcie_init_timeout_sw, FC350_PCIE_INIT_DELAY_US); stopwatch_init_usecs_expire(&pcie_init_timeout_sw, FC350_PCIE_INIT_DELAY_US);
printk(BIOS_DEBUG, "Bootblock configure eSPI\n"); printk(BIOS_DEBUG, "Bootblock configure eSPI\n");
dword = pm_read32(0x90); dword = pm_read32(PM_SPI_PAD_PU_PD);
dword |= 1 << 16; dword |= PM_ESPI_CS_USE_DATA2;
pm_write32(0x90, dword); pm_write32(PM_SPI_PAD_PU_PD, dword);
dword = pm_read32(0x74); dword = pm_read32(PM_ACPI_CONF);
dword |= 3 << 10; dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL;
pm_write32(0x74, dword); pm_write32(PM_ACPI_CONF, dword);
} }
void bootblock_mainboard_init(void) void bootblock_mainboard_init(void)

13
src/mainboard/google/guybrush/verstage.c
View File

@ -5,6 +5,7 @@
#include <arch/io.h> #include <arch/io.h>
#include <baseboard/variants.h> #include <baseboard/variants.h>
#include <security/vboot/vboot_common.h> #include <security/vboot/vboot_common.h>
#include <soc/southbridge.h>
static void setup_gpio(void) static void setup_gpio(void)
{ {
@ -29,12 +30,12 @@ void verstage_mainboard_early_init(void)
if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) {
uint32_t dword; uint32_t dword;
printk(BIOS_DEBUG, "Verstage configure eSPI\n"); printk(BIOS_DEBUG, "Verstage configure eSPI\n");
dword = pm_io_read32(0x90); dword = pm_io_read32(PM_SPI_PAD_PU_PD);
dword |= 1 << 16; dword |= PM_ESPI_CS_USE_DATA2;
pm_io_write32(0x90, dword); pm_io_write32(PM_SPI_PAD_PU_PD, dword);
dword = pm_io_read32(0x74); dword = pm_io_read32(PM_ACPI_CONF);
dword |= 3 << 10; dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL;
pm_io_write32(0x74, dword); pm_io_write32(PM_ACPI_CONF, dword);
} }
} }