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mb/google/rex: Redirect AP UART over LPSS UART 0 

This patch ensures AP UART messages are coming over LPSS UART 0 hence,
select required kconfig and program both early and late UART
RX/TX GPIOs accroding to the rex schematics dated 06/27.

BUG=b:224325352
TEST=Able to see AP UART log over LPSS UART0.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7daa8200d1a7cf825dfdfed538573efd57ab2d97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65454
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2022-06-27 18:43:57 +05:30
parent a26760c047
commit abc59fb6fc
2 changed files with 9 additions and 0 deletions
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1
src/mainboard/google/rex/Kconfig
View File

@ -3,6 +3,7 @@ config BOARD_GOOGLE_REX_COMMON
select BOARD_ROMSIZE_KB_32768 select BOARD_ROMSIZE_KB_32768
select HAVE_ACPI_RESUME select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES
select INTEL_LPSS_UART_FOR_CONSOLE
config BOARD_GOOGLE_BASEBOARD_REX config BOARD_GOOGLE_BASEBOARD_REX
def_bool n def_bool n

8
src/mainboard/google/rex/variants/baseboard/rex/gpio.c
View File

@ -7,11 +7,19 @@
/* Pad configuration in ramstage */ /* Pad configuration in ramstage */
static const struct pad_config gpio_table[] = { static const struct pad_config gpio_table[] = {
/* ToDo: Fill gpio configuration */ /* ToDo: Fill gpio configuration */
/* H8 : UART0_RXD ==> UART_DBG_TX_SOC_RX */
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
/* H9 : UART0_TXD ==> UART_DBG_RX_SOC_TX */
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
}; };
/* Early pad configuration in bootblock */ /* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
/* ToDo: Fill early gpio configuration */ /* ToDo: Fill early gpio configuration */
/* H8 : UART0_RXD ==> UART_DBG_TX_SOC_RX */
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
/* H9 : UART0_TXD ==> UART_DBG_RX_SOC_TX */
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
}; };
const struct pad_config *__weak variant_gpio_table(size_t *num) const struct pad_config *__weak variant_gpio_table(size_t *num)