mb/google/rambi: add expresso variant
This variant was inadvertently missed when upstreaming other rambi
variants, so add it here for completeness. Add ACPI for the light
sensor to common code to match all other i2c devices.
Sourced from downstream Google branch firmware-expresso-5216.223.B,
commit 6f4073c0e8c8 ("baytrail: implement baytrail technical advisory
556192").
Change-Id: Ia507f95f6af85344e1ab8452f7b3c2cc61526699
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Matt DeVillier
Felix Held
parent
9dcdec5c2f
commit
abd561b717
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@ -32,6 +32,11 @@ config BOARD_GOOGLE_ENGUARDE
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select INTEL_GMA_HAVE_VBT
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select SYSTEM_TYPE_LAPTOP
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config BOARD_GOOGLE_EXPRESSO
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select BOARD_GOOGLE_BASEBOARD_RAMBI
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select INTEL_GMA_HAVE_VBT
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select SYSTEM_TYPE_LAPTOP
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config BOARD_GOOGLE_GLIMMER
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select BOARD_GOOGLE_BASEBOARD_RAMBI
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select INTEL_GMA_HAVE_VBT
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@ -99,6 +104,7 @@ config VARIANT_DIR
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default "candy" if BOARD_GOOGLE_CANDY
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default "clapper" if BOARD_GOOGLE_CLAPPER
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default "enguarde" if BOARD_GOOGLE_ENGUARDE
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default "expresso" if BOARD_GOOGLE_EXPRESSO
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default "glimmer" if BOARD_GOOGLE_GLIMMER
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default "gnawty" if BOARD_GOOGLE_GNAWTY
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default "heli" if BOARD_GOOGLE_HELI
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@ -117,6 +123,7 @@ config MAINBOARD_PART_NUMBER
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default "Candy" if BOARD_GOOGLE_CANDY
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default "Clapper" if BOARD_GOOGLE_CLAPPER
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default "Enguarde" if BOARD_GOOGLE_ENGUARDE
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default "Expresso" if BOARD_GOOGLE_EXPRESSO
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default "Glimmer" if BOARD_GOOGLE_GLIMMER
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default "Gnawty" if BOARD_GOOGLE_GNAWTY
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default "Heli" if BOARD_GOOGLE_HELI
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@ -12,6 +12,9 @@ config BOARD_GOOGLE_CLAPPER
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config BOARD_GOOGLE_ENGUARDE
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bool "-> Enguarde"
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config BOARD_GOOGLE_EXPRESSO
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bool "-> Expresso"
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config BOARD_GOOGLE_GLIMMER
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bool "-> Glimmer (Lenovo ThinkPad 11e Chromebook)"
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@ -0,0 +1,35 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <variant/onboard.h>
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Scope (\_SB.PCI0.I2C5)
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{
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Device (ALSI)
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{
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Name (_HID, EisaId ("LSD2918"))
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Name (_DDN, "Intersil 29018 Ambient Light Sensor")
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Name (_UID, 1)
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Name (_CRS, ResourceTemplate()
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{
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I2cSerialBus (
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0x44, // SlaveAddress
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ControllerInitiated, // SlaveMode
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400000, // ConnectionSpeed
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AddressingMode7Bit, // AddressingMode
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"\\_SB.I2C5", // ResourceSource
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)
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Interrupt (ResourceConsumer, Edge, ActiveLow)
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{
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BOARD_ALS_IRQ
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}
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})
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Method (_STA)
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{
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If (\S5EN == 1) {
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Return (0xF)
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} Else {
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Return (0x0)
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}
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}
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}
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}
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@ -0,0 +1,16 @@
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## SPDX-License-Identifier: GPL-2.0-only
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# Order matters for SPD sources. The following indicies
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# define the SPD data to use.
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# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
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# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
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# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
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# 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz
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# 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
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# 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
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SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125
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SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
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SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125
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SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA
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SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125
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SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
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Binary file not shown.
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@ -0,0 +1,216 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <soc/gpio.h>
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#include <mainboard/google/rambi/irqroute.h>
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/* NCORE GPIOs */
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static const struct soc_gpio_map gpncore_gpio_map[] = {
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GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */
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GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */
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GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */
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GPIO_NC, /* S0_NC03 - NC */
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GPIO_NC, /* S0_NC04 - NC */
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GPIO_NC, /* S0_NC05 - NC */
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GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */
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GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */
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GPIO_NC, /* S0_NC08 - NC */
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GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */
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GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */
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GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */
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GPIO_NC, /* S0_NC12 - NC */
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GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */
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GPIO_NC, /* S0_NC14 - NC */
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GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */
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GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */
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GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */
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GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */
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GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */
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GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */
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GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */
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GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */
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GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */
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GPIO_NC, /* S0_NC24 - NC */
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GPIO_NC, /* S0_NC25 - NC */
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GPIO_NC, /* S0_NC26 - NC */
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GPIO_END
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};
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/* SCORE GPIOs */
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static const struct soc_gpio_map gpscore_gpio_map[] = {
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GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */
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GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */
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GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */
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GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */
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GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */
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GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */
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GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */
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GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */
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GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */
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GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */
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GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */
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GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */
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GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */
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GPIO_NC, /* S0-SC013 - NC */
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GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */
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GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */
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GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */
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GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */
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GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */
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GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */
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GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */
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GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */
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GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */
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GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */
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GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */
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GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */
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GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */
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GPIO_NC, /* S0-SC027 - NC */
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GPIO_NC, /* S0-SC028 - NC */
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GPIO_NC, /* S0-SC029 - NC */
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GPIO_NC, /* S0-SC030 - NC */
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GPIO_NC, /* S0-SC031 - NC */
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GPIO_NC, /* S0-SC032 - NC */
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GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */
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GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */
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GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */
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GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */
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GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */
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GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */
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GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */
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GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */
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GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */
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GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */
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GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */
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GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */
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GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */
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GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */
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GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */
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GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */
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GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */
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GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */
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GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */
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GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */
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GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */
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GPIO_DEFAULT, /* S0-SC054 - NC */
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GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */
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GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */
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GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */
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GPIO_INPUT, /* S0-SC058 - SIM_DET_C */
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GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */
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GPIO_NC, /* S0-SC060 - NC */
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GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */
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GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */
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GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */
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GPIO_FUNC1, /* S0-SC064 - I2S_DIN */
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GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */
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GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */
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GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */
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GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */
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GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */
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GPIO_DIRQ, /* S0-SC070 - ALS_INT_L - INT */
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GPIO_NC, /* S0-SC071 - NC */
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GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */
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GPIO_NC, /* S0-SC073 - NC */
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GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */
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GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */
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GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */
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GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */
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GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */
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GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */
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GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */
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GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */
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GPIO_NC, /* S0-SC082 - NC */
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GPIO_NC, /* S0-SC083 - NC */
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GPIO_NC, /* S0-SC084 - NC */
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GPIO_NC, /* S0-SC085 - NC */
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GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */
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GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */
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GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */
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GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */
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GPIO_NC, /* S0-SC090 - NC */
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GPIO_NC, /* S0-SC091 - NC */
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GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */
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GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */
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GPIO_NC, /* S0-SC094 - NC */
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GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */
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GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */
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GPIO_NC, /* S0-SC097 - NC */
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GPIO_NC, /* S0-SC098 - NC */
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GPIO_NC, /* S0-SC099 - NC */
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GPIO_NC, /* S0-SC100 - NC */
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GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */
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GPIO_END
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};
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/* SSUS GPIOs */
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static const struct soc_gpio_map gpssus_gpio_map[] = {
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GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */
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GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */
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GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */
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GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */
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GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */
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GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */
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GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */
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GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */
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GPIO_NC, /* S508 - NC */
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GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */
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GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */
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GPIO_FUNC0, /* S511 - SUSPWRDNACK */
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GPIO_FUNC0, /* S512 - WIFI_SUSCLK */
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GPIO_FUNC0, /* S513 - SLP_SX */
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GPIO_NC, /* S514 - NC */
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GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */
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GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */
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GPIO_NC, /* S517 - NC */
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GPIO_FUNC0, /* S518 - SUS_STAT# */
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GPIO_FUNC0, /* S519 - USB_OC0# */
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GPIO_FUNC0, /* S520 - USB_OC1# */
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GPIO_NC, /* S521 - NC */
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GPIO_NC, /* S522 - XDP_GPIO_DFX0 */
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GPIO_NC, /* S523 - XDP_GPIO_DFX1 */
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GPIO_NC, /* S524 - XDP_GPIO_DFX2 */
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GPIO_NC, /* S525 - XDP_GPIO_DFX3 */
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GPIO_NC, /* S526 - XDP_GPIO_DFX4 */
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GPIO_NC, /* S527 - XDP_GPIO_DFX5 */
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GPIO_NC, /* S528 - XDP_GPIO_DFX6 */
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GPIO_NC, /* S529 - XDP_GPIO_DFX7 */
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GPIO_NC, /* S530 - XDP_GPIO_DFX8 */
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GPIO_NC, /* S531 - NC */
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GPIO_NC, /* S532 - NC */
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GPIO_NC, /* S533 - NC */
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GPIO_NC, /* S534 - NC */
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GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */
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GPIO_NC, /* S536 - NC */
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GPIO_INPUT, /* S537 - RAM_ID0 */
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GPIO_INPUT, /* S538 - RAM_ID1 */
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GPIO_INPUT, /* S539 - RAM_ID2 */
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GPIO_NC, /* S540 - NC */
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GPIO_NC, /* S541 - NC */
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GPIO_NC, /* S542 - NC */
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GPIO_NC, /* S543 - NC */
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GPIO_END
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};
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static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {
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[TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO,
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[TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO,
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[I8042_IRQ_OFFSET] = I8042_IRQ_GPIO,
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[ALS_IRQ_OFFSET] = ALS_IRQ_GPIO,
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};
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static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {
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[CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO,
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};
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static struct soc_gpio_config gpio_config = {
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.ncore = gpncore_gpio_map,
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.score = gpscore_gpio_map,
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.ssus = gpssus_gpio_map,
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.core_dirq = &core_dedicated_irq,
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.sus_dirq = &sus_dedicated_irq,
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};
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struct soc_gpio_config *mainboard_get_gpios(void)
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{
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return &gpio_config;
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}
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@ -0,0 +1,30 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#define DPTF_CPU_PASSIVE 80
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#define DPTF_CPU_CRITICAL 90
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#define DPTF_TSR0_SENSOR_ID 1
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#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal"
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#define DPTF_TSR0_PASSIVE 48
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#define DPTF_TSR0_CRITICAL 70
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#define DPTF_TSR1_SENSOR_ID 2
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#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top"
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#define DPTF_TSR1_PASSIVE 60
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#define DPTF_TSR1_CRITICAL 70
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#define DPTF_TSR2_SENSOR_ID 3
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||||
#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom"
|
||||
#define DPTF_TSR2_PASSIVE 55
|
||||
#define DPTF_TSR2_CRITICAL 70
|
||||
|
||||
#define DPTF_ENABLE_CHARGER
|
||||
|
||||
/* Charger performance states, board-specific values from charger and EC */
|
||||
Name (CHPS, Package () {
|
||||
Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */
|
||||
Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
|
||||
Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
|
||||
Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
|
||||
Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */
|
||||
})
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* Atmel trackpad */
|
||||
#include <mainboard/google/rambi/acpi/trackpad_atmel.asl>
|
||||
|
||||
/* Atmel touchscreen */
|
||||
#include <mainboard/google/rambi/acpi/touchscreen_atmel.asl>
|
||||
|
||||
/* Intersil ALS */
|
||||
#include <mainboard/google/rambi/acpi/als_intersil.asl>
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
/* SPDX-License-Identifier: CC-PDDC */
|
||||
|
||||
/* Please update the license if adding licensable material. */
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef ONBOARD_H
|
||||
#define ONBOARD_H
|
||||
|
||||
#include <mainboard/google/rambi/irqroute.h>
|
||||
|
||||
/* PCH wake signal from EC. */
|
||||
#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0)
|
||||
|
||||
#define BOARD_TRACKPAD_NAME "trackpad"
|
||||
#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET)
|
||||
#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1)
|
||||
#define BOARD_TRACKPAD_I2C_BUS 0
|
||||
#define BOARD_TRACKPAD_I2C_ADDR 0x4b
|
||||
|
||||
#define BOARD_TOUCHSCREEN_NAME "touchscreen"
|
||||
#define BOARD_TOUCHSCREEN_IRQ GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET)
|
||||
#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2)
|
||||
#define BOARD_TOUCHSCREEN_I2C_BUS 5
|
||||
#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a
|
||||
|
||||
#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET)
|
||||
#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET)
|
||||
#define BOARD_ALS_IRQ GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET)
|
||||
|
||||
#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef VARIANT_H
|
||||
#define VARIANT_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* RAM_ID[2:0] are on GPIO_SSUS[39:37]
|
||||
* 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
|
||||
* 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
|
||||
* 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
|
||||
* 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz
|
||||
* 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
|
||||
* 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
|
||||
*/
|
||||
|
||||
static const uint32_t dual_channel_config =
|
||||
(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3);
|
||||
|
||||
#define SPD_SIZE 256
|
||||
#define GPIO_SSUS_37_PAD 57
|
||||
#define GPIO_SSUS_38_PAD 50
|
||||
#define GPIO_SSUS_39_PAD 58
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
chip soc/intel/baytrail
|
||||
|
||||
# Allow PCIe devices to wake system from suspend
|
||||
register "pcie_wake_enable" = "1"
|
||||
|
||||
device domain 0 on
|
||||
device pci 18.5 on end # I2C5
|
||||
device pci 18.6 on end # I2C6
|
||||
device pci 1c.1 on end # PCIE_PORT2
|
||||
end
|
||||
end
|
||||
Loading…
Reference in New Issue