intel/haswell,broadwell: Rename EMRR to PRMRR
The MSRs were already named as PRMRR in broadwell, just mismatching with the rest of the code. All later devices use the names PRMRR and UNCORE_PRMRR for these MSRs. Reflect the name change in structures and local variables. Change-Id: Id825ba2c083d0def641dd9bf02d3b671d85b1e35 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34825 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Kyösti Mälkki
parent
d53fd704f2
commit
abddb1fff0
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@ -31,10 +31,10 @@
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#include <southbridge/intel/lynxpoint/pch.h>
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#include "haswell.h"
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#define EMRRphysBase_MSR 0x1f4
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#define EMRRphysMask_MSR 0x1f5
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#define UNCORE_EMRRphysBase_MSR 0x2f4
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#define UNCORE_EMRRphysMask_MSR 0x2f5
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#define MSR_PRMRR_PHYS_BASE 0x1f4
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#define MSR_PRMRR_PHYS_MASK 0x1f5
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#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4
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#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5
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#define SMM_MCA_CAP_MSR 0x17d
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#define SMM_CPU_SVRSTR_BIT 57
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#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32))
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@ -45,7 +45,7 @@
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#define IEDBASE_MSR 0xc22
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#define SMRR_SUPPORTED (1 << 11)
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#define EMRR_SUPPORTED (1 << 12)
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#define PRMRR_SUPPORTED (1 << 12)
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struct smm_relocation_params {
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u32 smram_base;
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@ -54,10 +54,10 @@ struct smm_relocation_params {
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u32 ied_size;
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msr_t smrr_base;
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msr_t smrr_mask;
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msr_t emrr_base;
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msr_t emrr_mask;
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msr_t uncore_emrr_base;
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msr_t uncore_emrr_mask;
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msr_t prmrr_base;
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msr_t prmrr_mask;
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msr_t uncore_prmrr_base;
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msr_t uncore_prmrr_mask;
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/* The smm_save_state_in_msrs field indicates if SMM save state
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* locations live in MSRs. This indicates to the CPUs how to adjust
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* the SMMBASE and IEDBASE */
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@ -75,22 +75,22 @@ static inline void write_smrr(struct smm_relocation_params *relo_params)
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wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
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}
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static inline void write_emrr(struct smm_relocation_params *relo_params)
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static inline void write_prmrr(struct smm_relocation_params *relo_params)
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{
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printk(BIOS_DEBUG, "Writing EMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->emrr_base.lo, relo_params->emrr_mask.lo);
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wrmsr(EMRRphysBase_MSR, relo_params->emrr_base);
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wrmsr(EMRRphysMask_MSR, relo_params->emrr_mask);
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printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo);
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wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base);
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wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask);
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}
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static inline void write_uncore_emrr(struct smm_relocation_params *relo_params)
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static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params)
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{
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printk(BIOS_DEBUG,
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"Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->uncore_emrr_base.lo,
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relo_params->uncore_emrr_mask.lo);
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wrmsr(UNCORE_EMRRphysBase_MSR, relo_params->uncore_emrr_base);
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wrmsr(UNCORE_EMRRphysMask_MSR, relo_params->uncore_emrr_mask);
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"Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->uncore_prmrr_base.lo,
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relo_params->uncore_prmrr_mask.lo);
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wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base);
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wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask);
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}
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static void update_save_state(int cpu, uintptr_t curr_smbase,
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@ -198,17 +198,17 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
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/* Make appropriate changes to the save state map. */
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update_save_state(cpu, curr_smbase, staggered_smbase, relo_params);
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/* Write EMRR and SMRR MSRs based on indicated support. */
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/* Write PRMRR and SMRR MSRs based on indicated support. */
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mtrr_cap = rdmsr(MTRR_CAP_MSR);
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if (mtrr_cap.lo & SMRR_SUPPORTED)
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write_smrr(relo_params);
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if (mtrr_cap.lo & EMRR_SUPPORTED) {
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write_emrr(relo_params);
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/* UNCORE_EMRR msrs are package level. Therefore, only
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if (mtrr_cap.lo & PRMRR_SUPPORTED) {
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write_prmrr(relo_params);
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/* UNCORE_PRMRR msrs are package level. Therefore, only
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* configure these MSRs on the BSP. */
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if (cpu == 0)
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write_uncore_emrr(relo_params);
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write_uncore_prmrr(relo_params);
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}
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}
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@ -228,8 +228,8 @@ static void fill_in_relocation_params(struct device *dev,
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u32 tseg_size;
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u32 tsegmb;
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u32 bgsm;
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u32 emrr_base;
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u32 emrr_size;
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u32 prmrr_base;
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u32 prmrr_size;
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int phys_bits;
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/* All range registers are aligned to 4KiB */
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const u32 rmask = ~((1 << 12) - 1);
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@ -261,24 +261,24 @@ static void fill_in_relocation_params(struct device *dev,
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| MTRR_PHYS_MASK_VALID;
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params->smrr_mask.hi = 0;
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/* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */
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emrr_base = (params->ied_base + (2 << 20)) & rmask;
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emrr_size = params->ied_size - (2 << 20);
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/* The PRMRR and UNCORE_PRMRR are at IEDBASE + 2MiB */
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prmrr_base = (params->ied_base + (2 << 20)) & rmask;
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prmrr_size = params->ied_size - (2 << 20);
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/* EMRR has 46 bits of valid address aligned to 4KiB. It's dependent
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/* PRMRR has 46 bits of valid address aligned to 4KiB. It's dependent
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* on the number of physical address bits supported. */
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params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK;
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params->emrr_base.hi = 0;
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params->emrr_mask.lo = (~(emrr_size - 1) & rmask)
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params->prmrr_base.lo = prmrr_base | MTRR_TYPE_WRBACK;
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params->prmrr_base.hi = 0;
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params->prmrr_mask.lo = (~(prmrr_size - 1) & rmask)
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| MTRR_PHYS_MASK_VALID;
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params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1;
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params->prmrr_mask.hi = (1 << (phys_bits - 32)) - 1;
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/* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */
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params->uncore_emrr_base.lo = emrr_base;
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params->uncore_emrr_base.hi = 0;
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params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) |
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/* UNCORE_PRMRR has 39 bits of valid address aligned to 4KiB. */
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params->uncore_prmrr_base.lo = prmrr_base;
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params->uncore_prmrr_base.hi = 0;
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params->uncore_prmrr_mask.lo = (~(prmrr_size - 1) & rmask) |
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MTRR_PHYS_MASK_VALID;
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params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1;
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params->uncore_prmrr_mask.hi = (1 << (39 - 32)) - 1;
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}
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static void setup_ied_area(struct smm_relocation_params *params)
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@ -301,7 +301,7 @@ static void setup_ied_area(struct smm_relocation_params *params)
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/* According to the BWG MP init section 2MiB of memory at IEDBASE +
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* 2MiB should be zeroed as well. However, I suspect what is intended
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* is to clear the memory covered by EMRR. TODO(adurbin): figure out if
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* is to clear the memory covered by PRMRR. TODO(adurbin): figure out if
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* this is really required.
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*/
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//memset(ied_base + (2 << 20), 0, (2 << 20));
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@ -87,6 +87,6 @@
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/* MTRR_CAP_MSR bits */
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#define SMRR_SUPPORTED (1<<11)
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#define EMRR_SUPPORTED (1<<12)
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#define PRMRR_SUPPORTED (1<<12)
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#endif
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@ -27,10 +27,10 @@ struct smm_relocation_params {
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u32 ied_size;
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msr_t smrr_base;
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msr_t smrr_mask;
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msr_t emrr_base;
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msr_t emrr_mask;
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msr_t uncore_emrr_base;
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msr_t uncore_emrr_mask;
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msr_t prmrr_base;
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msr_t prmrr_mask;
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msr_t uncore_prmrr_base;
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msr_t uncore_prmrr_mask;
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/* The smm_save_state_in_msrs field indicates if SMM save state
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* locations live in MSRs. This indicates to the CPUs how to adjust
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* the SMMBASE and IEDBASE */
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@ -44,22 +44,22 @@ static inline void write_smrr(struct smm_relocation_params *relo_params)
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wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
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}
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static inline void write_emrr(struct smm_relocation_params *relo_params)
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static inline void write_prmrr(struct smm_relocation_params *relo_params)
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{
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printk(BIOS_DEBUG, "Writing EMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->emrr_base.lo, relo_params->emrr_mask.lo);
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wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->emrr_base);
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wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->emrr_mask);
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printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo);
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wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base);
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wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask);
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}
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static inline void write_uncore_emrr(struct smm_relocation_params *relo_params)
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static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params)
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{
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printk(BIOS_DEBUG,
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"Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->uncore_emrr_base.lo,
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relo_params->uncore_emrr_mask.lo);
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wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_emrr_base);
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wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_emrr_mask);
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"Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->uncore_prmrr_base.lo,
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relo_params->uncore_prmrr_mask.lo);
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wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base);
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wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask);
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}
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static void update_save_state(int cpu, uintptr_t curr_smbase,
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@ -167,17 +167,17 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
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/* Make appropriate changes to the save state map. */
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update_save_state(cpu, curr_smbase, staggered_smbase, relo_params);
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/* Write EMRR and SMRR MSRs based on indicated support. */
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/* Write PRMRR and SMRR MSRs based on indicated support. */
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mtrr_cap = rdmsr(MTRR_CAP_MSR);
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if (mtrr_cap.lo & SMRR_SUPPORTED)
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write_smrr(relo_params);
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if (mtrr_cap.lo & EMRR_SUPPORTED) {
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write_emrr(relo_params);
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/* UNCORE_EMRR msrs are package level. Therefore, only
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if (mtrr_cap.lo & PRMRR_SUPPORTED) {
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write_prmrr(relo_params);
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/* UNCORE_PRMRR msrs are package level. Therefore, only
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* configure these MSRs on the BSP. */
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if (cpu == 0)
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write_uncore_emrr(relo_params);
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write_uncore_prmrr(relo_params);
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}
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}
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@ -197,8 +197,8 @@ static void fill_in_relocation_params(struct device *dev,
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u32 tseg_size;
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u32 tsegmb;
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u32 bgsm;
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u32 emrr_base;
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u32 emrr_size;
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u32 prmrr_base;
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u32 prmrr_size;
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int phys_bits;
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/* All range registers are aligned to 4KiB */
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const u32 rmask = ~((1 << 12) - 1);
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@ -230,24 +230,24 @@ static void fill_in_relocation_params(struct device *dev,
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| MTRR_PHYS_MASK_VALID;
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params->smrr_mask.hi = 0;
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/* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */
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emrr_base = (params->ied_base + (2 << 20)) & rmask;
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emrr_size = params->ied_size - (2 << 20);
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/* The PRMRR and UNCORE_PRMRR are at IEDBASE + 2MiB */
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prmrr_base = (params->ied_base + (2 << 20)) & rmask;
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prmrr_size = params->ied_size - (2 << 20);
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/* EMRR has 46 bits of valid address aligned to 4KiB. It's dependent
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/* PRMRR has 46 bits of valid address aligned to 4KiB. It's dependent
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* on the number of physical address bits supported. */
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params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK;
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params->emrr_base.hi = 0;
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params->emrr_mask.lo = (~(emrr_size - 1) & rmask)
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params->prmrr_base.lo = prmrr_base | MTRR_TYPE_WRBACK;
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params->prmrr_base.hi = 0;
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params->prmrr_mask.lo = (~(prmrr_size - 1) & rmask)
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| MTRR_PHYS_MASK_VALID;
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params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1;
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params->prmrr_mask.hi = (1 << (phys_bits - 32)) - 1;
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/* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */
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params->uncore_emrr_base.lo = emrr_base;
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params->uncore_emrr_base.hi = 0;
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params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) |
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/* UNCORE_PRMRR has 39 bits of valid address aligned to 4KiB. */
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params->uncore_prmrr_base.lo = prmrr_base;
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params->uncore_prmrr_base.hi = 0;
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params->uncore_prmrr_mask.lo = (~(prmrr_size - 1) & rmask) |
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MTRR_PHYS_MASK_VALID;
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params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1;
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params->uncore_prmrr_mask.hi = (1 << (39 - 32)) - 1;
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}
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static void setup_ied_area(struct smm_relocation_params *params)
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