arm64: Add support for secure monitor
Secure monitor runs at EL3 and is responsible for jumping to the payload at specified EL and also to manage features like PSCI. Adding basic implementation of secure monitor as a rmodule. Currently, it just jumps to the the payload at current EL. Support for switching el and PSCI will be added as separate patches. CQ-DEPEND=CL:218300 BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles succesfully and secure monitor loads and runs payload on ryu Change-Id: If0f22299a9bad4e93311154e5546f5bae3f3395c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5e40a21115aeac1cc3c73922bdc3e42d4cdb7d34 Original-Change-Id: I86d5e93583afac141ff61475bd05c8c82d17d926 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214371 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9080 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Furquan Shaikh
Patrick Georgi
parent
ab020f304e
commit
abde3b56ce
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@ -63,7 +63,7 @@ subdirs-y += site-local
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#######################################################################
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# Add source classes and their build options
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classes-y := ramstage romstage bootblock smm smmstub cpu_microcode verstage
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classes-y := ramstage romstage bootblock smm smmstub cpu_microcode verstage secmon
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# Add dynamic classes for rmodules
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$(foreach supported_arch,$(ARCH_SUPPORTED), \
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@ -15,4 +15,9 @@ config ARCH_RAMSTAGE_ARM64
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bool
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default n
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config ARCH_USE_SECURE_MONITOR
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bool
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default n
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select RELOCATABLE_MODULES
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source src/arch/arm64/armv8/Kconfig
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@ -129,6 +129,12 @@ rmodules_arm64-y += ../../lib/memset.c
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rmodules_arm64-y += ../../lib/memcpy.c
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rmodules_arm64-y += ../../lib/memmove.c
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rmodules_arm64-y += eabi_compat.c
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secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += stage_entry.S
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secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += ../../lib/memset.c
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secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += ../../lib/memcmp.c
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secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += ../../lib/memcpy.c
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ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
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ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
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@ -21,6 +21,8 @@
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subdirs-y += lib/
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subdirs-$(CONFIG_ARCH_USE_SECURE_MONITOR) += secmon/
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armv8_flags = -march=armv8-a -I$(src)/arch/arm64/include/armv8/ -D__COREBOOT_ARM_ARCH__=8
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armv8_asm_flags = $(armv8_flags)
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@ -71,6 +73,8 @@ ramstage-y += cpu.S
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ramstage-y += exception.c
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ramstage-y += mmu.c
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ramstage-$(CONFIG_ARCH_USE_SECURE_MONITOR) += secmon_loader.c
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ramstage-c-ccopts += $(armv8_flags)
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ramstage-S-ccopts += $(armv8_asm_flags)
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@ -32,4 +32,9 @@ endif
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ifeq ($(CONFIG_ARCH_RAMSTAGE_ARMV8_64),y)
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ramstage-y += $(lib_access)
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ifeq ($(CONFIG_ARCH_USE_SECURE_MONITOR),y)
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secmon-y += $(lib_access)
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endif
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endif
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@ -0,0 +1,49 @@
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################################################################################
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2014 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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################################################################################
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$(eval $(call create_class_compiler,secmon,arm64))
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SECMON_DIR=$(obj)/arch/arm64/armv8/secmon
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SECMON_SRC=$(SECMON_DIR)/secmon
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SECMON_OBJ=$(SECMON_DIR)/secmon.o
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SECMON_ELF=$(SECMON_DIR)/secmon.elf
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SECMON_RMOD=$(SECMON_DIR)/secmon.elf.rmod
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SECMON_RAMSTAGE=$(SECMON_DIR)/secmon.ramstage.o
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secmon-c-ccopts += -I$(src)/arch/arm64/include/armv8/ -include $(src)/include/kconfig.h -D__SECMON__
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secmon-S-ccopts += -I$(src)/arch/arm64/include/armv8/ -include $(src)/include/kconfig.h -D__SECMON__
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secmon-y += secmon_init.c
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secmon-y += ../../transition_asm.S ../../transition.c
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ramstage-srcs += $(SECMON_SRC)
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$(SECMON_OBJ): $$(secmon-objs)
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$(CC_secmon) $(LDFLAGS) -nostdlib -r -o $@ $^
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$(eval $(call rmodule_link,$(SECMON_ELF), $(SECMON_OBJ), 0,arm64))
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$(SECMON_SRC): $(SECMON_RMOD)
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$(OBJCOPY_secmon) -O binary $< $@
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$(SECMON_RAMSTAGE): $(SECMON_SRC)
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@printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
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cd $(dir $@); $(OBJCOPY_secmon) -I binary $(notdir $<) -O elf64-littleaarch64 -B aarch64 $(notdir $@)
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@ -0,0 +1,83 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <arch/barrier.h>
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#include <arch/io.h>
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#include <arch/lib_helpers.h>
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#include <arch/secmon.h>
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#include <arch/transition.h>
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#include <console/console.h>
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#include <rmodule.h>
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#include <stddef.h>
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static void secmon_wait(void)
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{
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/*
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* TODO(furquan): This should be a point of no-return. Once we have PSCI
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* support we need to respond to kernel calls
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*/
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while (1)
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wfe();
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}
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static void secmon_el3_init(void)
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{
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uint32_t scr;
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scr = raw_read_scr_el3();
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/* Enable SMC */
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scr &= ~(SCR_SMC_MASK);
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scr |= SCR_SMC_ENABLE;
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raw_write_scr_el3(scr);
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isb();
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}
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static void secmon_init(void *arg)
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{
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struct exc_state exc_state;
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struct secmon_params *params = arg;
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printk(BIOS_DEBUG, "ARM64: secmon in %s\n", __func__);
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secmon_el3_init();
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/*
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* Check if the arg is non-NULL
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* 1) If yes, we make an EL2 transition to that entry point
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* 2) If no, we just wait
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*/
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if (params == NULL) {
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secmon_wait();
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}
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memset(&exc_state, 0, sizeof(exc_state));
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exc_state.elx.spsr = get_eret_el(params->elx_el, params->elx_mode);
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transition_with_entry(params->entry, params->arg, &exc_state);
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}
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/*
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* This variable holds entry point for secmon init code. Once the stacks are
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* setup by the stage_entry.S, it jumps to c_entry.
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*/
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void (*c_entry)(void*) = &secmon_init;
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@ -0,0 +1,111 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*
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* secmon_loader.c: Responsible for loading the rmodule, providing entry point
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* and parameter location for the rmodule.
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*/
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#include <arch/lib_helpers.h>
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#include <arch/secmon.h>
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#include <console/console.h>
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#include <rmodule.h>
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#include <string.h>
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/* SECMON entry point encoded as an rmodule */
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extern unsigned char _binary_secmon_start[];
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typedef void (*secmon_entry_t)(struct secmon_params *);
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void __attribute__((weak)) soc_get_secmon_base_size(uint64_t *secmon_base, size_t *secmon_size)
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{
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/* Default weak implementation initializes to 0 */
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*secmon_base = 0;
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*secmon_size = 0;
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}
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static secmon_entry_t secmon_load_rmodule(void)
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{
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struct rmodule secmon_mod;
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uint64_t secmon_base;
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size_t secmon_size;
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/* Get base address and size of the area available for secure monitor
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* rmodule.
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*/
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soc_get_secmon_base_size(&secmon_base, &secmon_size);
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if ((secmon_base == 0) || (secmon_size == 0)) {
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printk(BIOS_ERR, "ARM64: secmon_base / secmon_size invalid\n");
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return NULL;
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}
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printk(BIOS_DEBUG,"secmon_base:%lx,secmon_size:%lx\n",
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(unsigned long)secmon_base, (unsigned long)secmon_size);
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/* Fail if can't parse secmon module */
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if (rmodule_parse(&_binary_secmon_start, &secmon_mod)) {
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printk(BIOS_ERR, "ARM64: secmon_mod not found\n");
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return NULL;
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}
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/* Load rmodule at secmon_base */
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if (rmodule_load((void *)secmon_base, &secmon_mod)) {
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printk(BIOS_ERR, "ARM64:secmon_mod cannot load\n");
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return NULL;
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}
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/* Identify the entry point for secure monitor */
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return rmodule_entry(&secmon_mod);
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}
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void secmon_run(void (*entry)(void *), void *cb_tables)
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{
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struct secmon_params params;
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uint32_t scr;
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printk(BIOS_SPEW, "payload jump @ %p\n", entry);
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if (get_current_el() != EL3) {
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printk(BIOS_DEBUG, "Secmon Error: Can only be loaded in EL3\n");
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return;
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}
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secmon_entry_t doit = secmon_load_rmodule();
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if (doit == NULL)
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die("ARM64 Error: secmon load error");
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printk(BIOS_DEBUG, "ARM64: Loaded the el3 monitor...jumping to %p\n",
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doit);
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params.entry = entry;
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params.arg = cb_tables;
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params.elx_el = EL2;
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params.elx_mode = SPSR_USE_L;
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/* We want to enforce the following policies:
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* NS bit is set for lower EL
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*/
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scr = raw_read_scr_el3();
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scr |= SCR_NS;
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raw_write_scr_el3(scr);
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doit(¶ms);
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}
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@ -19,6 +19,7 @@
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#include <arch/cache.h>
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#include <arch/lib_helpers.h>
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#include <arch/secmon.h>
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#include <arch/stages.h>
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#include <arch/transition.h>
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#include <cbmem.h>
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@ -28,17 +29,20 @@
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void arch_payload_run(const struct payload *payload)
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{
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void (*doit)(void *) = payload->entry;
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void (*payload_entry)(void *) = payload->entry;
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void *cb_tables = cbmem_find(CBMEM_ID_CBTABLE);
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uint8_t current_el = get_current_el();
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printk(BIOS_SPEW, "entry = %p\n", payload->entry);
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secmon_run(payload_entry, cb_tables);
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/* If current EL is not EL3, jump to payload at same EL. */
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if (current_el != EL3) {
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cache_sync_instructions();
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/* Point of no-return */
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doit(cb_tables);
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payload_entry(cb_tables);
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}
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/* If current EL is EL3, we transition to payload in EL2. */
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@ -0,0 +1,43 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __ARCH_ARM64_ARMV8_SECMON__
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#define __ARCH_ARM64_ARMV8_SECMON__
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#include <arch/cpu.h>
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#if IS_ENABLED(CONFIG_ARCH_USE_SECURE_MONITOR)
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struct secmon_params {
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void (*entry)(void *);
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void *arg;
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uint8_t elx_el;
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uint8_t elx_mode;
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};
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void secmon_run(void (*entry)(void *), void *arg);
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void soc_get_secmon_base_size(uint64_t *secmon_base, size_t *secmon_size);
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#else
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static inline void secmon_run(void (*entry)(void *), void *arg) {}
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#endif /* IS_ENABLED(CONFIG_ARCH_USE_SECURE_MONITOR) */
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#endif /*__ARCH_ARM64_ARMV8_SECMON__ */
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@ -18,3 +18,7 @@ romstage-y += die.c
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bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += vtxprintf.c printk.c
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bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += init.c console.c
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bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += die.c
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secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += vtxprintf.c printk.c
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secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += init.c console.c
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secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += die.c
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@ -43,6 +43,7 @@ void __attribute__ ((noreturn)) die(const char *msg);
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#define __CONSOLE_ENABLE__ \
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((ENV_BOOTBLOCK && CONFIG_BOOTBLOCK_CONSOLE) || \
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ENV_SECMON || \
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ENV_ROMSTAGE || ENV_RAMSTAGE || (ENV_SMM && CONFIG_DEBUG_SMI))
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#if __CONSOLE_ENABLE__
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@ -28,24 +28,35 @@
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#define ENV_ROMSTAGE 0
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#define ENV_RAMSTAGE 0
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#define ENV_SMM 0
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#define ENV_SECMON 0
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#elif defined(__PRE_RAM__)
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#define ENV_BOOTBLOCK 0
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#define ENV_ROMSTAGE 1
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#define ENV_RAMSTAGE 0
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#define ENV_SMM 0
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#define ENV_SECMON 0
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#elif defined(__SMM__)
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#define ENV_BOOTBLOCK 0
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#define ENV_ROMSTAGE 0
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#define ENV_RAMSTAGE 0
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#define ENV_SMM 1
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#else
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#define ENV_SECMON 0
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#elif defined(__SECMON__)
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#define ENV_BOOTBLOCK 0
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#define ENV_ROMSTAGE 0
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#define ENV_RAMSTAGE 0
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#define ENV_SMM 0
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#define ENV_SECMON 1
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#else
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#define ENV_BOOTBLOCK 0
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#define ENV_ROMSTAGE 0
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#define ENV_RAMSTAGE 1
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#define ENV_SMM 0
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#define ENV_SECMON 0
|
||||
#endif
|
||||
|
||||
/* For romstage and ramstage always build with simple device model, ie.
|
||||
|
|
|
|||
|
|
@ -120,6 +120,7 @@ bootblock-y += halt.c
|
|||
romstage-y += halt.c
|
||||
ramstage-y += halt.c
|
||||
smm-y += halt.c
|
||||
secmon-y += halt.c
|
||||
|
||||
ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
|
||||
ramstage-y += rmodule.c
|
||||
|
|
|
|||
Loading…
Reference in New Issue