From abe0d810f00927f1589e6f7909e898c211a30319 Mon Sep 17 00:00:00 2001
From: Sridhar Siricilla <sridhar.siricilla@intel.com>
Date: Wed, 23 Mar 2022 12:28:56 +0530
Subject: [PATCH] soc/intel/alderlake: Log CSE RO write protection info for ADL

The patch logs CSE RO's write protection information for Alder Lake
platform. As part of write protection information, coreboot logs status
on CSE RO write protection and range. Also, logs error message if EOM
is disabled, and write protection for CSE RO is not enabled.

TEST=Verify the write protection details on Gimble.

Excerpt from Gimble coreboot log:
	[DEBUG]  ME: WP for RO is enabled        : YES
	[DEBUG]  ME: RO write protection scope - Start=0x1000, End=0x15AFFF

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I766d5358bb7dd495b4a9b22a2f1b41dc90f3d8d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
---
 src/soc/intel/alderlake/me.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/src/soc/intel/alderlake/me.c b/src/soc/intel/alderlake/me.c
index ea949025a7..31b09da351 100644
--- a/src/soc/intel/alderlake/me.c
+++ b/src/soc/intel/alderlake/me.c
@@ -2,6 +2,7 @@
 
 #include <bootstate.h>
 #include <intelblocks/cse.h>
+#include <intelblocks/spi.h>
 #include <console/console.h>
 #include <soc/me.h>
 #include <stdint.h>
@@ -90,6 +91,25 @@ union me_hfsts6 {
 	} __packed fields;
 };
 
+static void log_me_ro_write_protection_info(bool mfg_mode)
+{
+	bool cse_ro_wp_en = is_spi_wp_cse_ro_en();
+
+	printk(BIOS_DEBUG, "ME: WP for RO is enabled        : %s\n",
+			cse_ro_wp_en ? "YES" : "NO");
+
+	if (cse_ro_wp_en) {
+		uint32_t base, limit;
+		spi_get_wp_cse_ro_range(&base, &limit);
+		printk(BIOS_DEBUG, "ME: RO write protection scope - Start=0x%X, End=0x%X\n",
+				base, limit);
+	}
+
+	/* If EOM is disabled, but CSE RO is not write protected, log error */
+	if (!mfg_mode && !cse_ro_wp_en)
+		printk(BIOS_ERR, "ME: Write protection for CSE RO is not enabled\n");
+}
+
 static void dump_me_status(void *unused)
 {
 	union me_hfsts1 hfsts1;
@@ -161,6 +181,9 @@ static void dump_me_status(void *unused)
 		hfsts6.fields.cpu_debug_disable ? "YES" : "NO");
 	printk(BIOS_DEBUG, "ME: TXT Support                 : %s\n",
 		hfsts6.fields.txt_support ? "YES" : "NO");
+
+	if (CONFIG(SOC_INTEL_CSE_LITE_SKU))
+		log_me_ro_write_protection_info(!!hfsts1.fields.mfg_mode);
 }
 
 BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL);